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NV34C02WF Scheda tecnica(PDF) 8 Page - ON Semiconductor

Il numero della parte NV34C02WF
Spiegazioni elettronici  EEPROM SPD 2-kb I2C
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Produttore elettronici  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NV34C02WF Scheda tecnica(HTML) 8 Page - ON Semiconductor

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NV34C02WF
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SLAVE
ADDRESS
S
N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
S
A
C
K
DATA n
SLAVE
ADDRESS
S
T
A
R
T
Figure 11. Selective Read Timing
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
Figure 12. Sequential Read Timing
Software Write Protection
The lower half of memory (first 128 bytes) can be
protected against Write requests by setting one of two
Software Write Protection (SWP) flags.
The Permanent Software Write Protection (PSWP) flag
can be set or read while all address pins are at regular CMOS
levels (GND or VCC), whereas the very high voltage VHV
must be present on address pin A0 to set, clear or read the
Reversible Software Write Protection (RSWP) flag. The
D.C. OPERATING CONDITIONS for RSWP operations
are shown in Table 7.
The SWP commands are listed in Table 8. All commands
are preceded by a START and terminated with a STOP,
following the ACK or NoACK from the NV34C02WF. All
SWP related Slave addresses use the pre−amble: 0110 (6h),
instead of the regular 1010 (Ah) used for memory access.
For PSWP commands, the three address pins can be at any
logic level, whereas for RSWP commands the address pins
must be at pre−assigned logic levels. VHV is interpreted as
logic ‘1’. The VHV condition must be established on pin A0
before the START and maintained just beyond the STOP.
Otherwise an RSWP request could be interpreted by the
NV34C02WF as a PSWP request.
The SWP Slave addresses follow the standard I2C
convention, i.e. to read the state of the SWP flag, the LSB of
the Slave address must be ‘1’, and to set or clear a flag, it
must be ‘0’. For Write commands a dummy byte address and
dummy data byte must be provided (Figure 14). In contrast
to a regular memory Read, a SWP Read does not return Data.
Instead the NV34C02WF will respond with NoACK if the
flag is set and with ACK if the flag is not set. Therefore, the
Master can immediately follow up with a STOP, as there is
no meaningful data following the ACK interval (Figure 15).
Hardware Write Protection
With the WP pin held HIGH, the entire memory, as well
as the SWP flags are protected against Write operations, see
Memory Protection Map below. If the WP pin is left floating
or is grounded, it has no impact on the operation of the
NV34C02WF.
The state of the WP pin is strobed on the last falling edge
of SCL immediately preceding the first data byte (Figure 9).
If the WP pin is HIGH during the strobe interval, the
NV34C02WF will not acknowledge the data byte and the
Write request will be rejected.
Software Write Protectable
(by setting the write
protect flags)
FFH
00H
7FH
Hardware Write Protectable
(by connecting WP pin to
VCC)
Figure 13. Memory Protection Map


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