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AD8344 Scheda tecnica(PDF) 3 Page - Analog Devices |
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AD8344 Scheda tecnica(HTML) 3 Page - Analog Devices |
3 / 20 page AD8344 Rev. 0 | Page 3 of 20 SPECIFICATIONS VS = 5 V, TA = 25°C, fRF = 890 MHz, fLO = 1090 MHz, LO power = 0 dBm, ZO = 50 Ω, RBIAS = 2.43 kΩ, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit RF INPUT INTERFACE (Pin 15, RFIN and Pin 14, RFCM) Return Loss 10 dB DC Bias Level Internally generated; port must be ac-coupled 2.6 V OUTPUT INTERFACE Output Impedance Differential impedance, f = 200 MHz 9||1 kΩ||pF DC Bias Voltage Externally generated 4.75 VS 5.25 V Power Range Via a 4:1 balun 13 dBm LO INTERFACE LO Power −10 0 +4 dBm Return Loss 10 dB DC Bias Voltage Internally generated; port must be ac-coupled VS − 1.6 V POWER-DOWN INTERFACE PWDN Threshold VS − 1.4 V PWDN Response Time Device enabled, IF output to 90% of its final level 0.4 µs Device disabled, supply current < 5 mA 0.01 µs PWDN Input Bias Current Device enabled −80 µA Device disabled 100 µA POWER SUPPLY Positive Supply Voltage 4.75 VS 5.25 V Quiescent Current VPDC Supply current for bias cells 5 mA VPMX, IFOP, IFOM Supply current for mixer, RBIAS = 2.43 kΩ 44 mA VPLO Supply current for LO limiting amplifier 35 mA Total Quiescent Current 73 84 95 mA Power-Down Current Device disabled 500 µA |
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