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KMM366S1623CTY Scheda tecnica(PDF) 6 Page - Samsung semiconductor |
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KMM366S1623CTY Scheda tecnica(HTML) 6 Page - Samsung semiconductor |
6 / 11 page PC100 SDRAM MODULE KMM366S1623CTY REV. 0 August 1998 Preliminary AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 3.3V 1200 Ω 870 Ω Output 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Vtt = 1.4V 50 Ω Output 50pF Z0 = 50 Ω (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit OPERATING AC PARAMETER 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Notes : • • • • (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note -H -L Row active to row active delay tRRD(min) 20 20 ns 1 RAS to CAS delay tRCD(min) 20 20 ns 1 Row precharge time tRP(min) 20 20 ns 1 Row active time tRAS(min) 50 50 ns 1 tRAS(max) 100 us Row cycle time tRC(min) 70 70 ns 1 Last data in to row precharge tRDL(min) 1 CLK 2 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 Number of valid output data CAS latency=3 2 ea 4 CAS latency=2 1 |
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