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DAC121S101 Scheda tecnica(PDF) 2 Page - National Semiconductor (TI) |
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DAC121S101 Scheda tecnica(HTML) 2 Page - National Semiconductor (TI) |
2 / 19 page Block Diagram 20114903 Pin Descriptions TSOT (SOT-23) Pin No. MSOP Pin No. Symbol Description 14 V OUT DAC Analog Output Voltage. 2 8 GND Ground reference for all on-chip circuitry. 31 V A Power supply and Reference input. Should be decoupled to GND. 47 D IN Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. 5 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. 6 5 SYNC Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 2, 3 NC No Connect. There is no internal connection to these pins. www.national.com 2 |
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