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LFX1200B-03F900C Scheda tecnica(PDF) 1 Page - Lattice Semiconductor

Il numero della parte LFX1200B-03F900C
Spiegazioni elettronici  The ispXPGA architecture
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Homepage  http://www.latticesemi.com
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1
xpga_04
ispXPGA Family
March 2003
Preliminary Data Sheet
TM
© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
■ Non-volatile, Infinitely Reconfigurable
• Instant-on - Powers up in microseconds via
on-chip E2CMOS® based memory
• No external configuration memory
• Excellent design security, no bit stream to intercept
• Reconfigure SRAM based logic in milliseconds
■ High Logic Density for System-level
Integration
• 139K to 1.25M system gates
• 160 to 496 I/O
• 1.8V, 2.5V, and 3.3V VCC operation
• Up to 414Kb sysMEM™ embedded memory
■ High Performance Programmable Function
Unit (PFU)
•Four LUT-4 per PFU supports wide and narrow
functions
• Dual flip-flops per LUT-4 for extensive pipelining
• Dedicated logic for adders, multipliers, multiplex-
ers, and counters
■ Variable-Length Interconnect Routing
Technology
• Optimum speed, power, and flexibility for logic
interconnections
■ Flexible Memory Resources
• Multiple sysMEM Embedded RAM Blocks
– Single port, Dual port, and FIFO operation
• 64-bit distributed memory in each PFU
– Single port, Double port, FIFO, and Shift
Register operation
■ Eight sysCLOCK™ Phase Locked Loops
(PLLs) for Clock Management
•True PLL technology
• 10MHz to 320MHz operation
• Clock multiplication and division
• Phase adjustment
• Shift clocks in 250ps steps
■ sysIO™ for High System Performance
• High speed memory support through SSTL and
HSTL
• Advanced buses supported through PCI, GTL+,
LVDS, BLVDS, and LVPECL
• Standard logic supported through LVTTL,
LVCMOS 3.3, 2.5, and 1.8
• Programmable drive strength for series termination
• Programmable bus maintenance
■ sysHSI™ Capability for Ultra Fast Serial
Communications
• Up to 850Mbps performance
• Up to 20 channels per device
• Built in Clock Data Recovery (CDR) and
Serialization and De-serialization (SERDES)
■ Flexible Programming, Reconfiguration,
and Testing
• IEEE 1532 and 1149.1 compliant
• Microprocessor configuration interface
• Program E2CMOS while operating from SRAM
Table 1. ispXPGA Family Selection Guide
ispXPGA 125
ispXPGA 200
ispXPGA 500
ispXPGA 1200
System Gates
139K
210K
476K
1.25M
PFUs
484
676
1764
3844
LUT-4s
1936
2704
7056
15376
Logic FFs
3.8K
5.4K
14.1K
30.7K
sysMEM Memory
92K
111K
184K
414K
Distributed Memory
30K
43K
112K
246K
EBR
20
24
40
90
sysHSI Channels
4
8
12
20
User I/O
160/176
160/208
336
496
Packaging
256 fpBGA
516 fpBGA1
256 fpBGA
516 fpBGA1
516 fpBGA1
900 fpBGA
680 fpSBGA1
900 fpBGA
1. Thermally enhanced package.
Note: LFX1200B/C is preliminary, LFX125/200/500B/C information is advanced.


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