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MTV012A Scheda tecnica(PDF) 11 Page - List of Unclassifed Manufacturers

Il numero della parte MTV012A
Spiegazioni elettronici  8051 Embedded CRT Monitor Controller Mask Version
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Produttore elettronici  ETC [List of Unclassifed Manufacturers]
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MTV012A Scheda tecnica(HTML) 11 Page - List of Unclassifed Manufacturers

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MYSON
TECHNOLOGY
MTV012A
MTV012A Revision 1.1 12/23/1998
11/14
MCTR
00h (w)
LS1
LS0
LDFIFO
M256
M128
ACK
P
S
INTEN
60h (w)
EHPR
EVPR
EHPL
EVPL
EHF
EVF
EFIFO
EMI
FIFO
70h (w)
FIFO7
FIFO6
FIFO5
FIFO4
FIFO3
FIFO2
FIFO1
FIFO0
WDT
80h (w)
WEN
WCLR
CLRDDC
DIV253
LVSEL
WDT2
WDT1
WDT0
SLVCTR
90h (w)
ENSLV
SLVsel
ESLVBI
ESLVMI
X
X
X
X
SLVSTUS
91h (r)
WADR
SLVS
SLVBI
SLVMI
X
X
X
X
SLVINT
91h (w)
X
X
X
SLVMI
X
X
X
X
SLVBUF
92h (r)
SLVbuf7
SLVbuf6
SLVbuf5
SLVbuf4
SLVbuf3
SLVbuf2
SLVbuf1
SLVbuf0
SLVADR
93h (w)
SLVadr7
SLVadr6
SLVadr5
SLVadr4
SLVadr3
SLVadr2
SLVadr1
X
MCTR (w) :
Master IIC interface control register.
LS1, LS0
= 11
→ FIFOL is the status which has a FIFO depth of < 5.
= 10
→ FIFOL is the status which has a FIFO depth of < 4.
= 01
→ FIFOL is the status which has a FIFO depth of < 3.
= 00
→ FIFOL is the status which has a FIFO depth of < 2.
LDFIFO
= 1
→ FIFO will be written while S/W reads MBUF.
M256
= 1
→ Disables host writing EEPROM when address is over 256.
M128
= 1
→ Disables host writing EEPROM when address is over 128.
ACK
= 1
→ In receiving mode, there is no acknowledgment by MTV012A.
= 0
→ In receiving mode, ACK is returned by MTV012A.
S, P
=
↑,0
→ Start condition when Master IIC is not transferring.
= X,
↑ → Stop condition when Master IIC is not transferring.
= 1,X
→ Will resume transfer after a read/write MBUF operation.
= X,0
→ Forces HSCL low and occupies the IIC bus.
* MTV012A uses a 100KHz clock to sample the S/P bit; any pulse should sustain at least 20us.
* A write/read MBUF operation can be recognized only after 10us of the MI flag's rising edge.
MSTUS (r) :
Master IIC interface status register.
SCLERR
= 1
→ The ISCL pin is pulled-low by other devices during the
transfer, and cleared when S=0.
DDC2
= 1
→ DDC2B is active.
= 0
→ MTV012A remains in DDC1 mode.
BERR
= 1
→ IIC bus error, no ACK received from the slave, updated every time
when slave sends ACK on the ISDA pin.
HFREQ
= 1
→ MTV012A detects a higher than 200Hz clock on the VSYNC pin.
FIFOH
= 1
→ FIFO high indicated.
FIFOL
= 1
→ FIFO low indicated.
BUSY
= 1
→ Host drives the HSCL pin to low.
* While writing FIFO, the FIFOH/FIFOL flag will reflect the FIFO condition after 30us.
INTFLG (w) :
Interrupt flag. An interrupt event will set its individual flag and, if the corresponding
interrupt enable bit is set, the 8051 INT1 source will be driven by a zero level. Software
MUST clear this register while serving the interrupt routine.
FIFOI
= 1
→ No action.
= 0
→ Clears FIFOI flag.
MI
= 1
→ No action.
= 0
→ Clears Master IIC bus interrupt flag (MI).
INTFLG (r) :
Interrupt flag.
FIFOI
= 1
→ Indicates the FIFO low condition; when EFIFO is set, MTV012A will be
interrupted by INT1.
MI
= 1
→ Indicates when a byte is sent/received to/from the IIC bus; when EEPI is
active, MTV012A will be interrupted by INT1.
INTEN (w) :
Interrupt enabler.
EFIFO = 1
→ Enables FIFO interrupt.


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