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AM41DL6408G70IS Scheda tecnica(PDF) 10 Page - SPANSION

Il numero della parte AM41DL6408G70IS
Spiegazioni elettronici  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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August 19, 2002
Am41DL6408G
9
P R E L I M INARY
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-3 lists the device bus operations, the
inputs and control levels they require, and the result-
ing output. The following subsections describe each of
these operations in further detail.
Am41DL640
8
G
70
I
T
TAPE AND REEL
T
=
7 inches
S=
13 inches
TEMPERATURE RANGE
I
=
Industrial (–40
°C to +85°C)
SPEED OPTION
See Product Selector Guide and Valid Combinations
PROCESS TECHNOLOGY
G
=
0.17 µm
SRAM DEVICE DENSITY
8=
8 Mbits
AMD DEVICE NUMBER/DESCRIPTION
Am41DL6408G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous
Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
Valid Combinations
Order Number
Package Marking
Am41DL6408G70I
T, S
M41000000G
Am41DL6408G85I
T, S
M41000000H
Am41DL6408G71I
T, S
M410000087


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