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LTM8055 Scheda tecnica(PDF) 16 Page - Linear Technology

Il numero della parte LTM8055
Spiegazioni elettronici  36VIN, 8.5A Buck-Boost 關Module Regulator
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Produttore elettronici  LINER [Linear Technology]
Homepage  http://www.linear.com
Logo LINER - Linear Technology

LTM8055 Scheda tecnica(HTML) 16 Page - Linear Technology

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LTM8055
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8055fb
For more information www.linear.com/LTM8055
2. Place the CIN capacitor as close as possible to the VIN
and GND connection of the LTM8055.
3. Place the COUT capacitor as close as possible to the
VOUT and GND connection of the LTM8055.
4. Minimize the trace resistance between the optional
outputcurrentsenseresistor,ROUT,andVOUT.Minimize
the loop area of the IOUT trace and the trace from VOUT
to ROUT.
5. Minimizethetraceresistancebetweentheoptionalinput
current sense resistor, RIN and VIN. Minimize the loop
area of the IIN trace and the trace from VIN to RIN.
6. Place the CIN and COUT capacitors such that their
ground current flow directly adjacent or underneath
the LTM8055.
7. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8055.
8. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 6. The LTM8055 can benefit from
the heat sinking afforded by vias that connect to internal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8055. However, these capacitors
can cause problems if the LTM8055 is plugged into a live
supply (see Linear Technology Application Note 88 for a
complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt-
age at the VIN pin of the LTM8055 can ring to more than
twice the nominal input voltage, possibly exceeding the
LTM8055’sratinganddamagingthepart.Iftheinputsupply
is poorly controlled or the LTM8055 is hot-plugged into an
energized supply, the input network should be designed
APPLICATIONS INFORMATION
Figure 6. Layout Showing Suggested External Components,
GND Plane and Thermal Vias
ROUT
OUTPUT
SENSE
VOUT SIGNAL VIA
GND
GND/THERMAL VIAS
GND
INPUT
RIN
INPUT
SENSE
8055 F06
COUT
VOUT
IOUT
VIN
CIN
SVIN
LL
RT
MODE SYNC
RUN
FB
IIN
IOUT
VOUT SIGNAL VIA


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