[AK4133]

015015325-E-02

2018/05

- 20 -

Case2: ILRCK and OLRCK are not input when the PDN pin=

“H”

Case 2

External clocks

(Input port)

SDTI

SDTO

Normal

operation

< 20.2ms

Normal data

(No Clock)

External clocks

(Output port)

PDN

Power-down

Don

’t care

Don

’t care

Don

’t care

“0” data

LDO Up

Input Clocks

Input Data

Output Clocks

“0” data

(Don

’t care)

(Don

’t care)

SRCE_N

(3)

wait ILRCK

(1)

(2)

(4)

Ratio detection

& GD

LDO: Internal Regurator

GD: Group Delay

< 5ms

Figure 17. System Reset Case2

(1) The SDTO pin outputs

“L” and the SRCE_N pin outputs “H” when the PDN pin= “L”.

(2) The internal regulator is powered up by PDN pin =

“H” and wait for ILRCK and OLRCK.

(3) SRC circuit is powered up and sampling frequency ratio detection starts when ILRCK and OLRCK

are input. SDTO output starts after group delay period when the frequency ratio detection is

completed. Until then, the SDTO output is

“L” and the SRCE_N pin outputs “H”. The time until SDTO

output becomes enabled after ILRCK and OLPCK input is 20.2msec (Max.).

(4) The SRCE_N pin outputs

“L” when SDTO data output becomes enabled.