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AK4132 Scheda tecnica(PDF) 22 Page - Asahi Kasei Microsystems |
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AK4132 Scheda tecnica(HTML) 22 Page - Asahi Kasei Microsystems |
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22 / 27 page  [AK4132] 015015036-E-03 2018/05 - 22 - 15. Recommended External Circuits Figure 19 and Figure 20 show the system connection diagram. Figure 19. Typical Connection Diagram (Output Port: Master Mode, Regulator: Enable) Figure 20. Typical Connection Diagram (Output Port: Slave mode, Regulator: Disable) ODIF IDIF CM TEST ILRCK IBICK SDTI OMCLK 6 5 4 3 2 DSP1 Mater Clock AK4132 Top View Control Control + 0.1 10 Digital 3.3V 10 0.1 + Regulator: Enable Output PORT: Master Mode 7 8 1 PDN VSEL DVDD DVSS VD18 SDTO OBICK OLRCK 11 12 13 14 15 10 9 16 DSP2 ODIF IDIF CM TEST ILRCK IBICK SDTI OMCLK 6 5 4 3 2 DSP1 AK4132 Top View Control Control + 0.1 10 Digital 1.8V 10 0.1 + 7 8 1 PDN VSEL DVDD DVSS VD18 SDTO OBICK OLRCK 11 12 13 14 15 10 9 16 DSP2 Digital 1.8V Regulator: Disable Output PORT: Slave Mode |
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