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ADC08D500 Scheda tecnica(PDF) 1 Page - Analog Devices

Il numero della parte ADC08D500
Spiegazioni elettronici  High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
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ADC08D500
High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D
Converter
General Description
The ADC08D500 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 800 MSPS. Consum-
ing a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt
supply, this device is guaranteed to have no missing codes
over the full operating temperature range. The unique folding
and interpolating architecture, the fully differential compara-
tor design, the innovative design of the internal sample-and-
hold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters beyond Nyquist,
producing a high 7.5 ENOB with a 250 MHz input signal and
a 500 MHz sample rate while providing a 10
-18 B.E.R. Output
formatting is offset binary and the LVDS digital outputs are
compliant with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved
and used as a single 1 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40˚C
≤ T
A
≤ +85˚C) temperature range.
Features
n
Internal Sample-and-Hold
n
Single +1.9V ±0.1V Operation
n
Choice of SDR or DDR output clocking
n
Interleave Mode for 2x Sampling Rate
n
Multiple ADC Synchronization Capability
n
Guaranteed No Missing Codes
n
Serial Interface for Extended Control
n
Fine Adjustment of Input Full-Scale Range and Offset
n
Duty Cycle Corrected Sample Clock
Key Specifications
n
Resolution
8 Bits
n
Max Conversion Rate
500 MSPS (min)
n
Bit Error Rate
10
-18 (typ)
n
ENOB @ 250 MHz Input
7.5 Bits (typ)
n
DNL
±0.15 LSB (typ)
n
Power Consumption
— Operating
1.4 W (typ)
— Power Down Mode
3.5 mW (typ)
Applications
n
Direct RF Down Conversion
n
Digital Oscilloscopes
n
Satellite Set-top boxes
n
Communications Systems
n
Test Instrumentation
Block Diagram
20121453
May 2005
© 2005 National Semiconductor Corporation
DS201214
www.national.com


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