S29GL512N datasheet(69/92 Pages) CYPRESS

Il numero della parte	S29GL512N

Spiegazioni elettronici	512, 256, 128 Mbit, 3 V, Page Flash Featuring 110 nm MirrorBit

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Produttore elettronici	CYPRESS [Cypress Semiconductor]

Homepage	http://www.cypress.com

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69 / 92 page

Document Number: 002-01522 Rev. *B

Page 69 of 92

S29GL512N

S29GL256N

S29GL128N

Figure 15.2

Page Read Timings

Note

* Figure shows word mode. Addresses are A2–A-1 for byte mode.

15.2

Hardware Reset (RESET#)

Notes

1. Not 100% tested. If ramp rate is equal to or faster than 1V/100µs with a falling edge of the RESET# pin initiated, the RESET# pin needs to be held low only for 100µs

for power-up.

2. Next generation devices may have different reset speeds. To increase system design considerations, please refer to Advance Information on S29GL-P Hardware

Reset (RESET#) and Power-up Sequence on page 80 for advance reset speeds on S29GL-P devices.

Parameter

Description

Speed (Note 2)

Unit

JEDEC

Std.

tReady

RESET# Pin Low (During Embedded Algorithms) to

Read Mode (Note 1)

Max

20

ns

tReady

RESET# Pin Low (NOT During Embedded Algorithms)

to Read Mode (Note 1)

Max

500

ns

tRP

RESET# Pulse Width

Min

500

ns

tRH

Reset High Time Before Read (Note 1)

Min

50

ns

tRPD

RESET# Low to Standby Mode

Min

20

µs

tRB

RY/BY# Recovery Time

Min

0

ns

Amax-A2

CE#

OE#

A2-A0*

Data Bus

Same Page

Aa

Ab

Ac

Ad

Qa

Qb

Qc

Qd

tACC

tPACC

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