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ACT2861QI Scheda tecnica(PDF) 46 Page - Active-Semi, Inc |
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ACT2861QI Scheda tecnica(HTML) 46 Page - Active-Semi, Inc |
46 / 91 page ACT2861QI Rev 2.0, 27-Apr-2018 Innovative PowerTM www.active-semi.com ActiveSwitcherTM is a trademark of Active-Semi Copyright © 2018 Active-Semi, Inc. 46 Where COTG_IN is the OTG input capacitance (Charging output capacitance) in uF, IOTG is the OTG output cur- rent in Amperes, VOTG is the OTG output voltage in volts, Vin is the OTG input voltage in volts, FSW is the switching frequency in Hz, and Vripple is the maximum OTG input voltage ripple in volts. If the OTG input source is a battery, no additional ca- pacitance is needed. If the OTG input source is a power supply rail, add an additional 100uF bulk electrolytic ca- pacitor is recommended. The ceramic capacitor PCB placement is critical. Refer to the Layout Guidelines selection and to the EVK layout for details. Be sure to consider the input capacitor’s DC bias effects. A capacitor’s actual capacitance is strongly affected by its DC bias characteristics. The input capacitor is typi- cally an X5R, X7R, or similar dielectric. Use of Y5U, Z5U, or similar dielectrics is not recommended. Input capaci- tor placement is critical for proper operation. The input capacitor must be placed as close to the IC as possible. The traces from VBAT to the capacitor and from the ca- pacitor to PGND should as short and wide as possible. OTG – Output Capacitor Selection Note that the OTG COUT capacitors are also the charg- ing input capacitors. They are connected to VIN. The output capacitance must be a combination of ceramic and bulk capacitance. Table 9 gives the required capacitor values for stability. Note that the table has two output capacitor options: Standard Capacitance and Minimum Capacitance. The Standard Capacitance design requires more overall ca- pacitance, but places no restriction on the bulk capacitor ESR. The Minimum Capacitance design results in an overall smaller design, but places restrictions on the ESR. The capacitor values can be increased without limit. Note that the Ceramic and Bulk capacitor values are recommended “Capacitor Values”. When choosing the ceramic capacitors, use X5R or X7R dielectrics and be sure to consider the capacitor’s tolerance and DC bias effects. Use of Y5U, Z5U, or similar dielectrics is not recommended. The 22uF capacitor must have at least 9uF of effective capacitance for stability. The 47uF ca- pacitor must have 19uF of capacitance. The bulk capac- itors do not have DC bias effects. Output ceramic capacitor placement is critical for proper operation. The output capacitor must be placed as close to the IC as possible. The traces from VIN to the capac- itor and from the capacitor to PGND should as short and wide as possible. The bulk capacitor should be placed to the left of the current sense resistor. Refer to the Lay- out Guidelines selection and to the EVK layout for addi- tional details. OTG - Inductor Selection The buck-boost regulator utilizes current-mode control and a proprietary compensation scheme to simultane- ously compensate the buck, buck-boost, and boost modes of operation. The ACT2861 compensation re- quires a fixed inductor value that is matched to the switching frequency. Table 9 gives the required inductor value. Choose an inductor with a low DC-resistance, and avoid inductor saturation by choosing inductors with DC ratings that exceed the maximum output current by at least 30%. The inductor value must be within +30% to -30% across all operating conditions. OTG - Compensation The ACT2861 operates in three switching modes: buck, buck-boost, and boost mode depending on the input and output voltage ratios. The IC contains a proprietary compensation scheme to simultaneously compensate all three switching modes. The compensation values are directly tied to the switching frequency and required inductor value. Table 9 provides the required compen- sation values. Figure 16 shows the OTG compensation components. |
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