NCV59744

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2

Figure 2. Simplified Schematic Block Diagram

0.45

mA

Table 1. PIN FUNCTION DESCRIPTION

Name

QFN20

Description

IN

5−8

Unregulated input to the device.

EN

11

Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into

shutdown mode. This pin must not be left floating.

SS

15

Soft−Start pin. A capacitor connected on this pin to ground sets the start−up time. If this pin is left

floating, the regulator output soft−start ramp time is typically 200

ms.

BIAS

10

Bias input voltage for error amplifier, reference, and internal control circuits.

PG

9

threshold the pin is driven to a low−impedance state. A pull−up resistor from 10 k

W to 1 MW should be

connected from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage.

Alternatively, the PG pin can be left floating if output monitoring is not necessary.

FB

16

This pin is the feedback connection to the center tap of an external resistor divider network that sets the

output voltage. This pin must not be left floating.

OUT

1, 18−20

Regulated output voltage. It is recommended that the output capacitor

≥ 2.2 mF.

NC

2−4, 13, 14, 17

No connection. This pin can be left floating or connected to GND to allow better thermal contact to the

top−side plane.

GND

12

Ground

PAD/TAB

Should be soldered to the ground plane for increased thermal performance