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KM29U64000T Scheda tecnica(PDF) 3 Page - Samsung semiconductor |
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KM29U64000T Scheda tecnica(HTML) 3 Page - Samsung semiconductor |
3 / 26 page KM29U64000T, KM29U64000IT FLASH MEMORY 3 512B column 16 Byte Column Figure 1. FUNCTIONAL BLOCK DIAGRAM Figure 2. ARRAY ORGANIZATION NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is internally set to "Low" or "High" by the 00h or 01h Command. * X can be High or Low. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16 3rd Cycle A17 A18 A19 A20 A21 A22 *X *X VCC X-Buffers Y-Gating 64M + 2M Bit Command 2nd half Page Register & S/A NAND Flash ARRAY (512 + 16)Byte x 16384 Y-Gating 1st half Page Register & S/A I/O Buffers & Latches Latches & Decoders Y-Buffers Latches & Decoders Register Control Logic & High Voltage Generator Global Buffers Output Driver VSS A9 - A22 A0 - A7 Command CE RE WE CLE ALE WP I/0 0 I/0 7 VCCQ VSS A8 1st half Page Register (=256 Bytes) 2nd half Page Register (=256 Bytes) 16K Row (=1024 Block) 512 Byte 8 bit 16 Byte 1 Block(=16 Row) (8K + 256) Byte I/O 0 ~ I/O 7 1 Page = 528 Bytes 1 Block = 528 Bytes x 16 Pages = (8K + 256) Bytes 1 Device = 528 Bytes x 16Pages x 1024 Blocks = 66 Mbits Column Address Row Address (Page Address) Page Register |
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