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CS4231A-KQ Scheda tecnica(PDF) 7 Page - List of Unclassifed Manufacturers |
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CS4231A-KQ Scheda tecnica(HTML) 7 Page - List of Unclassifed Manufacturers |
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7 / 76 page  TIMING PARAMETERS (TA = 25 °C; VA1, VA2, VD1-VD4 = +5V, outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD4) Parameter Symbol Min Max Units WR or RD strobe width tSTW 90 ns Data valid to WR rising edge (write cycle) tWDSU 22 ns RD falling edge to data valid (read cycle) tRDDV 60 ns CS setup to WR of RD falling edge tCSSU 10 ns CS hold from WR or RD rising edge tCSHD 0ns ADDR <> setup to RD or WR falling edge tADSU 22 ns ADDR <> hold from WR or RD rising edge tADHD 10 ns DAK inactive to WR or RD falling edge (DMA cycle completion immediately followed by a non-DMA cycle) tSUDK1 60 ns DAK active from WR or RD rising edge (non-DMA cycle completion immediately followed by DMA cycle) tSUDK2 0ns DAK setup to RD falling edge (DMA cycles) DAK setup to WR falling edge tDKSUa tDKSUb 25 25 ns ns Data hold from WR rising edge tDHD2 15 ns DRQ hold from WR or RD falling edge (assumes no more DMA cycles needed) tDRHD 025 ns Time between rising edge of WR or RD to next falling edge of WR or RD tBWND 80 ns Data hold from RD rising edge tDHD1 020 ns DAK hold from WR rising edge DAK hold from RD rising edge tDKHDa tDKHDb 25 25 ns ns DBEN or DBDIR active from WR or RD falling edge tDBDL 40 ns PDWN pulse width low tPDWN 200 ns Crystals, XTAL1I, XTAL2I frequency (Notes 1,7,8) 25.6 MHz XTAL1I, XTAL2I high time (Notes 1,8) 18 ns XTAL1I, XTAL2I low time (Notes 1,8) 18 ns Sample frequency (Note 1) Fs 5.5 50 kHz Serial Port Timing SCLK frequency (Note 9) tSCLKW Fsx64 Hz SCLK rising to SDOUT valid tPD1 30 ns SCLK rising to FSYNC transition tPD2 -20 20 ns SDIN valid to SCLK falling tS1 30 ns SDIN hold after SCLK falling tH1 30 ns Notes: 7. When only one crystal is used, it must be XTAL1. When using two crystals, the high frequency crystal should be on XTAL1 which is designed for higher loop gains. 8. Sample frequency specifications must not be exceeded. 9. When SF1, 0 = 10, 32-bit mode, SCLK is active for the first 32 bit periods of the frame, and remains low during the last 32 bit periods of the frame. CS4231A DS139PP2 7 |
Codice articolo simile - CS4231A-KQ |
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Descrizione simile - CS4231A-KQ |
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