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IRFPS40N50L Scheda tecnica(PDF) 6 Page - Vishay Siliconix |
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IRFPS40N50L Scheda tecnica(HTML) 6 Page - Vishay Siliconix |
6 / 9 page www.vishay.com Document Number: 91260 6 S11-0111-Rev. C, 07-Feb-11 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Fig. 12d - Maximum Safe Operating Area Fig. 13a - Gate Charge Test Circuit Fig. 13b - Basic Gate Charge Waveform A R G IAS 0.01 Ω tp D.U.T. L VDS + - VDD Driver 15 V 20 V IAS VDS tp 1 10 100 1000 10 100 100 OPERATION IN THIS AREA LIMITED BY RDS(on) Single Pulse T T = 150 C = 25 C ° ° J C V , Drain-to-Source Voltage (V) DS 10us 100us 1ms 10ms 25 50 75 100 125 150 0 500 1000 1500 2000 Starting T , Junction Temperature( C) J ° ID TOP BOTTOM 21A 30A 46A D.U.T. 3 mA V GS V DS I G I D 0.3 µF 0.2 µF 50 k Ω 12 V Current regulator Current sampling resistors Same type as D.U.T. + - Q GS Q GD Q G VG Charge V GS |
Codice articolo simile - IRFPS40N50L_17 |
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Descrizione simile - IRFPS40N50L_17 |
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