CY7C1648KV18 datasheet(28/29 Pages) CYPRESS

Il numero della parte	CY7C1648KV18

Spiegazioni elettronici	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

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Produttore elettronici	CYPRESS [Cypress Semiconductor]

Homepage	http://www.cypress.com

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28 / 29 page

Document Number: 001-44061 Rev. *L

Page 28 of 29

CY7C1648KV18

CY7C1650KV18

*H (cont.)

3706738

08/08/2012

PRIT

Updated Pin Configurations (Removed CY7C1646KV18, CY7C1657KV18

related information).

Updated Pin Definitions (Removed CY7C1646KV18, CY7C1657KV18 related

information).

Updated Functional Overview (Removed CY7C1646KV18, CY7C1657KV18

related information).

Updated Truth Table (Removed CY7C1646KV18, CY7C1657KV18 related

information).

Updated Write Cycle Descriptions (Removed CY7C1646KV18 related

information).

Removed Write Cycle Descriptions (Corresponding to CY7C1657KV18).

Updated Identification Register Definitions (Removed CY7C1646KV18,

CY7C1657KV18 related information).

Updated Operating Range (Removed Industrial Temperature Range).

Updated Electrical Characteristics (Updated DC Electrical Characteristics

(Removed 375 MHz, 333 MHz frequencies related information, removed

values of IDD parameter and ISB1 parameter corresponding to × 18 for 450 MHz

frequency)).

Updated Switching Characteristics (Removed 375 MHz, 333 MHz frequencies

related information).

Updated Ordering Information (Updated part numbers).

*I

4372665

05/07/2014

PRIT

Updated Application Example:

Updated Figure 2.

Updated Thermal Resistance:

Updated values of

JA parameter.

Included

JB parameter and its details.

Updated to new template.

*J

4575228

11/20/2014

PRIT

Updated Functional Description:

Added “For a complete list of related documentation, click here.” at the end.

Updated Ordering Information:

Updated part numbers.

*K

5056316

12/18/2015

PRIT

Updated Package Diagram:

spec 51-85195 – Changed revision from *C to *D.

Updated to new template.

Completing Sunset Review.

*L

6013622

01/04/2018 AESATMP8 Updated logo and Copyright.

Document History Page (continued)

Document Title: CY7C1648KV18/CY7C1650KV18, 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read

Latency)

Document Number: 001-44061

Rev.

ECN No.

Submission

Date

Orig. of

Change

Description of Change

Codice articolo simile - CY7C1648KV18

Produttore elettronici	Il numero della parte	Scheda tecnica	Spiegazioni elettronici
Cypress Semiconductor	CY7C1648KV18-400BZXC	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
Cypress Semiconductor	CY7C1648KV18	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

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Descrizione simile - CY7C1648KV18

Produttore elettronici	Il numero della parte	Scheda tecnica	Spiegazioni elettronici
Cypress Semiconductor	CY7C1648KV18	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C1668KV18	771Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1548KV18	844Kb / 29P	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C2670KV18	824Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Renesas Technology Corp	R1QHA4436RBG	916Kb / 30P	144-Mbit DDR?줚I SRAM 2-word Burst Architecture (2.0 Cycle Read latency)
Cypress Semiconductor	CY7C2644KV18	840Kb / 30P	144-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
	CY7C1643KV18	861Kb / 31P	144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C2642KV18	885Kb / 30P	144-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
	CY7C1166KV18	874Kb / 29P	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1546KV18	959Kb / 31P	72-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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CY7C1648KV18 Scheda tecnica(PDF) 28 Page - Cypress Semiconductor

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