Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

CY7C1441KV33 Scheda tecnica(PDF) 22 Page - Cypress Semiconductor

Il numero della parte CY7C1441KV33
Spiegazioni elettronici  36-Mbit (1M36/2M18) Flow-Through SRAM (With ECC)
Download  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1441KV33 Scheda tecnica(HTML) 22 Page - Cypress Semiconductor

Back Button CY7C1441KV33 Datasheet HTML 18Page - Cypress Semiconductor CY7C1441KV33 Datasheet HTML 19Page - Cypress Semiconductor CY7C1441KV33 Datasheet HTML 20Page - Cypress Semiconductor CY7C1441KV33 Datasheet HTML 21Page - Cypress Semiconductor CY7C1441KV33 Datasheet HTML 22Page - Cypress Semiconductor CY7C1441KV33 Datasheet HTML 23Page - Cypress Semiconductor CY7C1441KV33 Datasheet HTML 24Page - Cypress Semiconductor CY7C1441KV33 Datasheet HTML 25Page - Cypress Semiconductor CY7C1441KV33 Datasheet HTML 26Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 32 page
background image
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Document Number: 001-66677 Rev. *I
Page 22 of 32
Switching Characteristics
Over the Operating Range
Parameter [18, 19]
Description
–133
Unit
Min
Max
tPOWER
VDD (Typical) to the first Access[20]
1
ms
Clock
tCYC
Clock cycle time
7.5
ns
tCH
Clock HIGH
2.5
ns
tCL
Clock LOW
2.5
ns
Output Times
tCDV
Data Output Valid after CLK Rise
6.5
ns
tDOH
Data Output Hold after CLK Rise
2.5
ns
tCLZ
Clock to Low Z[21, 22, 23]
2.5
ns
tCHZ
Clock to High Z[21, 22, 23]
3.8
ns
tOEV
OE LOW to Output Valid
3.0
ns
tOELZ
OE LOW to Output Low Z[21, 22, 23]
0
ns
tOEHZ
OE HIGH to Output High Z[21, 22, 23]
3.0
ns
Setup Times
tAS
Address setup before CLK Rise
1.5
ns
tADS
ADSP, ADSC setup before CLK Rise
1.5
ns
tADVS
ADV setup before CLK Rise
1.5
ns
tWES
GW, BWE, BWX setup before CLK Rise
1.5
ns
tDS
Data input setup before CLK Rise
1.5
ns
tCES
Chip Enable setup
1.5
ns
Hold Times
tAH
Address Hold after CLK Rise
0.5
ns
tADH
ADSP, ADSC Hold after CLK Rise
0.5
ns
tWEH
GW, BWE, BWX Hold after CLK Rise
0.5
ns
tADVH
ADV Hold after CLK Rise
0.5
ns
tDH
Data Input Hold after CLK Rise
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
ns
Notes
18. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
19. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
20. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be
initiated.
21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 21. Transition is measured ± 200 mV from steady-state voltage.
22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
23. This parameter is sampled and not 100% tested.


Codice articolo simile - CY7C1441KV33

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Cypress Semiconductor
CY7C1441KV25 CYPRESS-CY7C1441KV25 Datasheet
856Kb / 29P
   36-Mbit (1M 횞 36) Flow-Through SRAM
More results

Descrizione simile - CY7C1441KV33

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Cypress Semiconductor
CY7C1381KV33 CYPRESS-CY7C1381KV33 Datasheet
1Mb / 34P
   18-Mbit (512K 횞 36/1M 횞 18) Flow-Through SRAM (With ECC)
CY7C1461KV33 CYPRESS-CY7C1461KV33 Datasheet
2Mb / 23P
   36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM with NoBL??Architecture
CY7C1440KV33 CYPRESS-CY7C1440KV33 Datasheet
3Mb / 33P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined Sync SRAM (With ECC)
CY7C1441KV25 CYPRESS-CY7C1441KV25 Datasheet
856Kb / 29P
   36-Mbit (1M 횞 36) Flow-Through SRAM
CY7C1460KV25 CYPRESS-CY7C1460KV25 Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460KV33 CYPRESS-CY7C1460KV33 Datasheet
1,010Kb / 31P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1371KV33 CYPRESS-CY7C1371KV33 Datasheet
682Kb / 24P
   18-Mbit (512K 횞 36/1M 횞 18) Flow-Through SRAM with NoBL??Architecture (With ECC)
CY7C1460SV25 CYPRESS-CY7C1460SV25 Datasheet
429Kb / 31P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture
CY7C1444KV33 CYPRESS-CY7C1444KV33 Datasheet
1Mb / 22P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined DCD Sync SRAM
CY7C1370KV33 CYPRESS-CY7C1370KV33 Datasheet
999Kb / 32P
   18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com