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CY7C1441KV33 Scheda tecnica(PDF) 22 Page - Cypress Semiconductor |
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CY7C1441KV33 Scheda tecnica(HTML) 22 Page - Cypress Semiconductor |
22 / 32 page CY7C1441KV33 CY7C1443KV33 CY7C1441KVE33 Document Number: 001-66677 Rev. *I Page 22 of 32 Switching Characteristics Over the Operating Range Parameter [18, 19] Description –133 Unit Min Max tPOWER VDD (Typical) to the first Access[20] 1 – ms Clock tCYC Clock cycle time 7.5 – ns tCH Clock HIGH 2.5 – ns tCL Clock LOW 2.5 – ns Output Times tCDV Data Output Valid after CLK Rise – 6.5 ns tDOH Data Output Hold after CLK Rise 2.5 – ns tCLZ Clock to Low Z[21, 22, 23] 2.5 – ns tCHZ Clock to High Z[21, 22, 23] – 3.8 ns tOEV OE LOW to Output Valid – 3.0 ns tOELZ OE LOW to Output Low Z[21, 22, 23] 0 – ns tOEHZ OE HIGH to Output High Z[21, 22, 23] – 3.0 ns Setup Times tAS Address setup before CLK Rise 1.5 – ns tADS ADSP, ADSC setup before CLK Rise 1.5 – ns tADVS ADV setup before CLK Rise 1.5 – ns tWES GW, BWE, BWX setup before CLK Rise 1.5 – ns tDS Data input setup before CLK Rise 1.5 – ns tCES Chip Enable setup 1.5 – ns Hold Times tAH Address Hold after CLK Rise 0.5 – ns tADH ADSP, ADSC Hold after CLK Rise 0.5 – ns tWEH GW, BWE, BWX Hold after CLK Rise 0.5 – ns tADVH ADV Hold after CLK Rise 0.5 – ns tDH Data Input Hold after CLK Rise 0.5 – ns tCEH Chip Enable Hold after CLK Rise 0.5 – ns Notes 18. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 19. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 20. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 21. Transition is measured ± 200 mV from steady-state voltage. 22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions. 23. This parameter is sampled and not 100% tested. |
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