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CY2VC521-2 Scheda tecnica(PDF) 5 Page - Cypress Semiconductor |
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CY2VC521-2 Scheda tecnica(HTML) 5 Page - Cypress Semiconductor |
5 / 9 page CY2VC521-2 Document Number: 001-15599 Rev. *E Page 5 of 9 AC Electrical Characteristics[4, 6] Parameter Description Test Conditions Min Typ Max Unit FOUT Output Frequency – 216 – MHz PR Pull Range VIN = VDD to VSS, relative to frequency at VIN = 1.65V, across operating temperature and voltage range ±115 – – ppm TR, TF [7] Output Rise and Fall Times 20% and 80% of swing between steady state levels –– 0.5 ns TJ Period Jitter, RMS – 7 – ps TJitter(φ) RMS Phase Jitter (Random) 216 MHz carrier, integrated 12 kHz–20 MHz – 1.3 – ps PN Phase Noise 1 kHz offset from 216 MHz carrier – –95 – dBc/Hz 10 kHz offset from 216 MHz carrier – –120 – dBc/Hz 100 kHz offset from 216 MHz carrier – –127 – dBc/Hz 1 MHz offset from 216 MHz carrier – –123 – dBc/Hz 10 MHz offset from 216 MHz carrier – –130 – dBc/Hz TDC [8] Duty Cycle Measured at zero crossing point 45 50 55 % TLOCK Start-up Time Time for CLK to reach valid frequency measured from the time VDD = VDD (min.) –– 5 ms Notes 6. Outputs are terminated with 50 Ω between CLK and CLK#. Refer to Figure 2 on page 3. 7. Refer to Figure 6 on page 6. 8. Refer to Figure 7 on page 6. [+] Feedback |
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