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SN74AUP1T97YZPR Scheda tecnica(PDF) 5 Page - Texas Instruments |
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SN74AUP1T97YZPR Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 15 page SN74AUP1T97 SINGLESUPPLY VOLTAGE LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic configurations 1 2 3 6 5 4 B Y C VCC B A Figure 5. 157: 2-to-1 Data Selector/MUX When C is L, Y = B When C is H, Y = A 1 2 3 6 5 4 A Y C VCC C Y A Figure 6. 08: 2-Input AND Gate C Y B 1 2 3 6 5 4 A Y C VCC C Y B Figure 7. 14+32/14+00: 2-Input OR/NAND Gate With One Inverted Input 1 2 3 6 5 4 B Y C VCC Figure 8. 14+08/14+02: 2-Input AND/NOR Gate With One Inverted Input 1 2 3 6 5 4 B Y C VCC Figure 9. 32: 2-Input OR Gate C Y A C Y A C Y A GND GND GND C Y B GND 1 2 3 6 5 4 Y C VCC Figure 10. 04/14: Inverter Y C GND GND 1 2 3 6 5 4 Y VCC Figure 11. 17/34: Noninverted Buffer Y B GND B |
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