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ML145162EP Scheda tecnica(PDF) 3 Page - LANSDALE Semiconductor Inc. |
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ML145162EP Scheda tecnica(HTML) 3 Page - LANSDALE Semiconductor Inc. |
3 / 24 page www.lansdale.com Page 3 of 24 Issue 0 MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Rating Value Unit VDD DC Supply Voltage – 0.5 to + 6.0 V Vin Input Voltage, All Inputs – 0.5 to VDD + 0.5 V Iin, Iout DC Current Drain Per Pin 10 mA IDD, ISS DC Current Drain VDD or VSS Pins 30 mA Tstg Storage Temperature Range – 65 to + 150 ° C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA = 25°C) Guaranteed Limit Symbol Characteristic VDD Min Max Unit VDD Power Supply Voltage Range — 2.5 5.5 V VOL Output Voltage 0 Level (Iout = 0) 2.5 5.5 — — 0.1 0.1 V VOH (Vin =VDD or 0) 1 Level 2.5 5.5 2.45 5.45 — — VIL Input Voltage 0 Level (Vout = 0.5 V or VDD – 0.5 V) 2.5 5.5 — — 0.75 1.65 V VIH 1 Level 2.5 5.5 1.75 3.85 — — IOH Output Current (Vout = 2.2 V) Source (Vout = 5.0 V) 2.5 5.5 – 0.18 – 0.55 — — mA IOL (Vout = 0.3 V) Sink (Vout = 0.5 V) 2.5 5.5 0.18 0.55 — — IIL Input Current OSCin, fin–T, fin–R (Vin = 0) 2.5 5.5 — — – 30 – 66 µ A ADin, CLK, Din, ENB 2.5 5.5 — — – 1.0 – 1.0 IIH (Vin =VDD – 0.5) OSCin, fin–T, fin–R 2.5 5.5 — — 30 66 ADin, CLK, Din, ENB 2.5 5.5 — — 5.0 5.0 IOZ Three–State Leakage Current (Vout = 0 V or 5.5 V) 5.5 — ± 100 nA Cin Input Capacitance — — 8.0 pF Cout Output Capacitance — — 8.0 pF IDD(stdby) Standby Current (All Counters are in Power–Down Mode with Oscillator On) 2.5 5.5 — — 0.3 1.5 mA IDD Operating Current ML145162: 200 mV p–p input at f in–T and fin–R = 60 MHz 2.5 — 3.0 mA This device contains protection circuitry to guard against damage due to high static volt- ages or electric fields. However, precautions must be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused pins must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. LANSDALE Semiconductor, Inc. ML145162 |
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