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MC145159RP Scheda tecnica(PDF) 8 Page - LANSDALE Semiconductor Inc. |
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MC145159RP Scheda tecnica(HTML) 8 Page - LANSDALE Semiconductor Inc. |
8 / 10 page www.lansdale.com Page 8 of 10 Issue A LANSDALE Semiconductor, Inc. ML145159 DESIGN CONSIDERATIONS CRYSTAL OSCILLATOR CONSIDERATIONS The following options may be considered to provide a ref- erence frequency to Lansdale’s CMOS frequency synthesizers. Use of a Hybrid Crystal Oscillator Commercially available temperature–compensated crystal oscillators (TCXOs) or crystal–controlled data clock oscilla- tors provide very stable reference frequencies. An oscillator capable of sinking and sourcing 50 µA at CMOS logic levels may be direct or DC coupled to OSCin. In general, the highest frequency capability is obtained utilizing a direct coupled square wave having a rail–to–rail (VDD to VSS) voltage swing. If the oscillator does not have CMOS logic levels on the outputs, capacitive or AC coupling to OSCin may be used. OSCout, an unbuffered output, should be left floating. For additional information about TCXOs and data clock oscillators, please consult the latest version of the eem Electronic Engineers Master Catalog, the Gold Book, or simi- lar publications. Design an Off–Chip Reference The user may design an off–chip crystal oscillator using ICs specifically developed for crystal oscillator applications, such as the ML12061 MECL device. The reference signal from the MECL device is AC coupled to OSCin. For large amplitude signals (standard CMOS logic levels), DC coupling is used. OSCout, an unbuffered output, should be left floating. In gen- eral, the highest frequency capability is obtained with a direct–coupled square wave having rail–to–rail voltage swing. Use of the On–Chip Oscillator Circuitry The on–chip amplifier (a digital inverter) along with an ap- propriate crystal may be used to provide a reference source fre- quency. A fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in Figure 10. For VDD = 5 V, the crystal should be specified for a loading capacitance, CL, which does not exceed 32 pF for frequencies to approximately 8 MHz, 20 pF for frequencies in the area of 8 to 15 MHz, and 10 pF for higher frequencies. These are guide- lines that provide a reasonable compromise between IC capaci- tance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic CL values. Assuming R1 = 0 Ω. the shunt load capacitance, CL, presented across the crystal can be estimated to be: The oscillator can be “trimmed” on–frequency by making a portion or all of C1 variable. The crystal and associated com- ponents must be located as close as possible to the OSCin and OSCout pins to minimize distortion, stray capacitance, stray inductance, and start–up stabilization time. Circuit stray capac- itance can also be handled by adding the appropriate stray value to the values for Cin and Cout. For this approach, the term Cstray becomes zero in the above expression for CL. Power is dissipated in the effective series resistance of the crystal, Re, in Figure 12. The maximum drive level specified by the crystal manufacturer represents the maximum stress that a crystal can withstand without damaging or excessive shift in operating frequency. R1 in Figure 10 limits the drive level. The use of R1 is not necessary in most cases. To verify that the maximum dc supply voltage does not over- drive the crystal, monitor the output frequency as a function of voltage at OSCout. (Care should be taken to minimize load- ing.) The frequency should increase very slightly as the dc sup- ply voltage is increased. An overdriven crystal will decrease in frequency or become unstable with an increase in supply volt- age. The operating supply voltage must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the oscillator start–up time is proportion- al to the value of R1. Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful. See Table 1. CL = CinCout Cin + Cout + Ca + Cstray + C1 • C2 C1 + C2 where Cin = 5 pF (see Figure 11) Cout = 6 pF (see Figure 11) Ca = 1 pF (see Figure 11) C1 and C2 = external capacitors (see Figure 10) Cstray = the total equivalent external circuit stray capacitance appearing across the crystal terminals Figure 10. Pierce Crystal Oscillator Circuit * May be deleted in certain cases. See text. Figure 11. Parasitic Capacitances of the Amplifier and Cstray NOTE: Values are supplied by crystal manufacturer (parallel resonant crystal). Figure 12. Equivalent Crystal Networks |
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