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MC145145P1 Scheda tecnica(PDF) 6 Page - LANSDALE Semiconductor Inc. |
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MC145145P1 Scheda tecnica(HTML) 6 Page - LANSDALE Semiconductor Inc. |
6 / 12 page www.lansdale.com Page 6 of 12 LANSDALE Semiconductor, Inc. ML145145 PIN DESCRIPTIONS INPUT PINS D0 – D3 Data Inputs (PDIP – Pins 2, 1, 18, 17; SOG – Pins 2, 1, 20, 19) Information at these inputs is transferred to the internal latches when the ST input is in the high state. D3 is most sig- nigicant bit. fin Frequency Input (PDIP – Pin 3, SOG – Pin 4) Input to ÷N portion of synthesizer. fin is typically derived from the loop VCO and is ac couples. For larger amplitude sig- nals (standard CMOS – logic levels) dc coupling may be used. OSCin/OSCout Reference Oscillator Input/Output (PDIP – Pins 6, 7; SOG – Pins 7, 8) These pins form an on–chip reference oscillator when con- nected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be con- nected from OSCin to ground and OSCout to ground. OSCin may also serve as input for an externally–generated reference signal. This signal is typically AC coupled to OSCin but for larger amplitude signals (standard CMOS–logic levels) DC coupling may also be used. In the external refrence mode, no connection is required to OSCout. A0 – A2 Address Inputs (PDIP – Pins 8, 9, 10; SOG – Pins 9, 10, 12) A0, A1 and A2 are used to define which latch receives the information on the data input lines. The addresses refer to the following latches: ST Strobe Transfer (PDIP – Pin 11, SOG – Pin 13) The rising edge of strobe transfers data into the addressed latch, the falling edge of strobe latches data into the latch. This pin should normally be held low to avoid loading latches with invalid data. OUTPUT PINS PDout Single–Ended Phase Detector output (PDIP – Pin 12, SOG – Pin 14) Three–state output of phase detector for use as loop–error signal. Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High–Impedance State LD Lock Detector Signal (PDIP – Pin 13, SOG – Pin 15) High level when loop is locked (fR, fV of same phase and frequency). Pulses low when loop is out of lock. φV, φR Phase Detect or Outputs (PDIP – Pin 12, SOG – Pin 14) These phase detector outputs can be combined externally for a loop–error signal. A single–ended output is also available for this purpose (see PDout). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by φV pulsing low. φR remains essentially high. If the frequency of fV – fR and both are in phase, then both φV and φR remain high except for a small minimum time peri- od when both pulse low in phase. REFout Buffered Reference Output (DIP – Pin 16, SOG – Pin 18) Buffered output of on–chip reference oscillator or externally provided reference–input signal. POWER SUPPLY PINS VSS Ground (PDIP – Pin 4, SOG – Pin 5) Circuit Ground VDD Positive Power Supply (PDIP – Pin 5, SOG – Pin 6) The positive supply voltage may range from 3.0 to 9.0 V with respect to VSS. Issue b |
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