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ADC-304-3 Scheda tecnica(PDF) 3 Page - List of Unclassifed Manufacturers

Il numero della parte ADC-304-3
Spiegazioni elettronici  8-Bit, 20MHz, Low-Power Flash A/D Converters
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Produttore elettronici  ETC [List of Unclassifed Manufacturers]
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ADC-304-3 Scheda tecnica(HTML) 3 Page - List of Unclassifed Manufacturers

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ADC-304
®
®
6. The analog input signal is sampled on the positive-going
edge of CLOCK. Corresponding digital data appears at the
output on the negative-going edge of the CLOCK pulse after
a brief delay of 31ns maximum (TDLH, TDHL). Refer to the
Timing Diagram (Figure 3) for more information.
7. Connect all free pins to ANALOG GND to reduce unwanted
noise.
The analog input range is equal to a 2V spread. The
voltage on VT-VB will equal 2V. The connection of VT and
ANALOG GND is 2V higher than VB. Whether using a
single or dual power supply, the analog input will range from
the value of VT to VB. If VT equals +5V, then VB will equal
+3V and the analog input range will be from +3 to +5V.
4. The voltage between VT and VB is equivalent to the dynamic
range of the analog input. Bypass VB to ANALOG GND
USING a 1µF and a 0.01µF capacitor in parallel. To balance
the characteristics of the ADC-304 at high frequencies,
bypass VM with a 0.01µF capacitor to ANALOG GND.
Also, VM can be used as a trimming pin for more precise
linearity compensation. A stable voltage source with a
potential equal to VB and a 1k
Ω potentiometer can be
connected to VM as shown in Figure 2 for this purpose.
5. Separate the clock input, CLOCK, from other leads as much
as possible, observing proper EMI and RFI wiring
techniques. This reduces the inductive pick-up of this lead
from interfering with the “clean” operation of the ADC-304.
Figure 3. ADC-304 Timing Diagram
Figure 2.
Improving Linearity Compensation
VM
VB
0.01µF
+5V
1k
ANA GND
ANA GND
DUAL SUPPLY OPERATION
ADC-304
ADC-304
0.01µF
VM
VB
1k
0.01µF
SINGLE SUPPLY OPERATION
VB
VB
N DATA VALID
CLOCK
COMPARATOR
OUTPUT
Ta
N(1)
N(2)
N(3)
31ns max.
TDLH
TDHL
N(2) DATA VALID
N(1) DATA VALID
6-BIT LATCH OUTPUT
DATA OUTPUT
BITS 1-8
TPW0
TPW1
ANALOG
INPUT
22ns
max.
31ns max.
TDLH
TDHL
22ns
max.
3


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