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SLG46533 Scheda tecnica(PDF) 56 Page - Dialog Semiconductor |
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SLG46533 Scheda tecnica(HTML) 56 Page - Dialog Semiconductor |
56 / 185 page SLG46533_DS_114 Page 55 of 184 SLG46533 9.1.2 2-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings Table 45. DFF0 Register Settings Signal Function Register Bit Address Register Definition LUT2_0 or DFF0 Select reg <1191> 0: LUT2_0 1: DFF0 DFF0 Initial Polarity Select reg <1205> 0: Low 1: High DFF0 Output Select reg <1206> 0: Q output 1: nQ output DFF0 or Latch Select reg <1207> 0: DFF function 1: Latch function Table 46. DFF1 Register Settings Signal Function Register Bit Address Register Definition LUT2_1 or DFF1 Select reg <1190> 0: LUT2_1 1: DFF1 DFF1 Initial Polarity Select reg <1201> 0: Low 1: High DFF1 Output Select reg <1202> 0: Q output 1: nQ output Select or Latch select reg <1203> 0: DFF function 1: Latch function Table 47. DFF2 Register Settings Signal Function Register Bit Address Register Definition LUT2_2 or DFF2 Select reg <1189> 0: LUT2_2 1: DFF2 DFF2 Initial Polarity Select reg <1213> 0: Low 1: High DFF2 Output Select reg <1214> 0: Q output 1: nQ output DFF2 or Latch Select reg <1215> 0: DFF function 1: Latch function |
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