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SLG46531 Scheda tecnica(PDF) 90 Page - Dialog Semiconductor |
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SLG46531 Scheda tecnica(HTML) 90 Page - Dialog Semiconductor |
90 / 170 page SLG46531_DS_109 Page 89 of 169 SLG46531 10.2 ACMP0 Register Settings Table 83. ACMP0 Register Settings Signal Function Register Bit Address Register Definition ACMP0 Positive Input Source Select VDD reg<1172> 0: Disable 1: Enable ACMP0 Analog Buffer Enable reg<1173> 0: Disable analog buffer 1: Enable analog buffer ACMP0 Hysteresis Enable reg<1175:1174> 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) (01: for both external & internal VREF; 10 & 11: for only internal VREF; External VREF will not have 50mV & 200mV hysteresis.) ACMP0 Wake & Sleep function Enable reg<1490> 0: Disable 1: Enable ACMP0 In Voltage Select reg<1628:1624> 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN12) 11011: EXT_VREF(PIN7) 11100: EXT_VREF(PIN12)/2 11101: EXT_VREF(PIN7)/2 ACMP0 Positive Input Divider reg<1630:1629> 00: 1.00X 01: 0.50X 10: 0.33X 11: 0.25X ACMP0 Low Bandwidth (Max: 1 MHz) Enable reg<1631> 0: Off 1: On |
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