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SLG46200 Scheda tecnica(PDF) 63 Page - Dialog Semiconductor |
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SLG46200 Scheda tecnica(HTML) 63 Page - Dialog Semiconductor |
63 / 69 page 000-0046200-124 Page 58 of 64 SLG46200 reg<312:311> PIN 8 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<313> PIN 8 pull up/down resistor 0: Pull down resistor 1: Pull up resistor reg<314> PIN 8 open drain x2 enable 0: Disable 1: Enable reg<317:315> 3 DFFs or Latches selection 0: DFF function 1: Latch function reg<318> Source of digital comparators negative port selection control 0: DCOMP0 from reg<400:399>, DCOMP1 from reg<404:403> 1: From connection matrix out11 and out10 reg<319> S2P clock enable control 0: Disable 1: Enable reg<321:320> PIN 2 mode control 00: Digital in mode with Schmitt trigger 01: Digital in mode w/o Schmitt trigger 10: Low voltage digital in mode w/o Schmitt trigger (I/O pad supports input level 0.9V/1.2V/1.5V/1.8V) 11: Reserved reg<322> CNT2 14-bit input data selection 0: From NVM reg<460:447> 1: 6 most significant bits tie 0 and 8 less significant bits from S2P or ADC (controlled by reg<467> 0: from S2P<15:0>, 1:from ADC) reg<324:323> PIN 2 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<325> PIN 2 pull up/down resistor 0: Pull down resistor 1: Pull up resistor reg<328:326> PIN 3 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode w/o Schmitt trigger 010: Low voltage digital in mode w/o Schmitt trigger (I/O pad supports input level 0.9V/1.2V/1.5V/1.8V) 011: Reserved 100: Digital out current double mode when oe=1 101: Open drain mode 110: Push pull mode OE=0, output tri-state; OE=1, output enable 111: Reserved reg<330:329> PIN 3 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<331> PIN 3 pull up/down resistor 0: Pull down resistor 1: Pull up resistor Bit Address Definition |
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