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SLG46169 Scheda tecnica(PDF) 67 Page - Dialog Semiconductor |
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SLG46169 Scheda tecnica(HTML) 67 Page - Dialog Semiconductor |
67 / 102 page 000-0046169-105 Page 66 of 101 SLG46169 13.2 CNT/DLY0 Register Settings 13.3 CNT/DLY1 Register Settings Table 60. CNT/DLY0 Register Settings Signal Function Register Bit Address Register Definition Counter/Delay0 Mode Select reg<713> 0: Delay Mode 1: Counter Mode Counter/Delay0 Clock Source Select (external clock is only for counter mode) reg<716:714> 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter6 Overflow Counter0 Control Data/Delay0 Time Control reg<730:717> 1-16384: (delay time = (counter control data +2) /freq) Delay0 Mode Select reg<732:731> 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges Table 61. CNT/DLY1 Register Settings Signal Function Register Bit Address Register Definition Counter/Delay1 Mode Select reg<733> 0: Delay Mode 1: Counter Mode Counter/Delay1 Clock Source select reg<736:734> 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter0 Overflow Counter1 Control Data/Delay1 Time Control reg<750:737> 1-16384: (delay time = (counter control data +2) /freq) Delay1 Mode Select or asynchronous counter reset reg<752:751> 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter reset) 10: Delay on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode |
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