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SLG46140 Scheda tecnica(PDF) 98 Page - Dialog Semiconductor |
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SLG46140 Scheda tecnica(HTML) 98 Page - Dialog Semiconductor |
98 / 170 page 000-0046140-109 Page 97 of 169 SLG46140 13.2 ACMP0 Register Settings Table 68. ACMP0 Register Settings Signal Function Register Bit Address Register Definition ACMP0 In Voltage Select reg<500:496> 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: vref_ext_acmp1 11011: vref_ext_acmp0 11100: vref_ext_acmp1 / 2 11101: vref_ext_acmp0 / 2 11100: DAC1_out 11111: DAC0_out ACMP0 Hysteresis Enable reg<511:510> 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) ACMP0 Positive Input Divider reg<523:522> 00: 1.00X 01: 0.50X 10: 0.33X 11: 0.25X ACMP0 Low Bandwidth (Max: 1 MHz) Enable reg<524> 1: On 0: Off ACMP0 Positive Input Source Select reg<526:525> 00: Pin10 input 01: ADC PGA out 10: VDD 11: None ACMP0 input 100u Current Source Enable reg<540> 0: Disable 1: Enable |
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