10

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FAN5026 Rev. 1.0.5

Figure 9. Optimal 90° Phasing for DDR2

Initialization and Soft Start

Assuming EN is high, FAN5026 is initialized when VCC

exceeds the rising UVLO threshold. Should VCC drop

below the UVLO threshold, an internal Power-On Reset

function disables the chip.

The voltage at the positive input of the error amplifier is

limited by the voltage at the SS pin which is charged with

a 5

(0.9V) the output voltage will be in regulation. The time it

takes SS to reach 0.9V is:

When SS reaches 1.5V, the Power Good outputs are

enabled and hysteretic mode is allowed. The converter is

forced into PWM mode during soft start.

Current Processing Section

The following discussion refers to Figure 10.

shortly after Q2 is turned on. That current is held, and

summed with the output of the error amplifier. This effec-

tively creates a current mode control loop. The resistor

current feedback loop. For stable operation, the voltage

induced by the current feedback at the PWM comparator

input should be set to 30% of the ramp amplitude at

maximum load current and line voltage. The following

Figure 10. Current Limit / Summing Circuits

VDDQ

VTT

CLK

(1)

T

0.9

0.9

C

SS

×

5

-------------------------

=

(2a)

R

SENSE

I

LOAD MAX

•

•

30%

0.125

V

IN MAX

()

•

•

-----------------------------------------------------------------------------

100

–

=

(2b)

R

SENSE MIN

()

I

LOAD MAX

()

•

150

µA

-----------------------------------------------------------

100

–

=

LDRV

PGND

ISNS

in +

in –

2.5V

ILIM det.

R

SENSE

SS

1.5M

C

SS

VSEN

V to I

Reference and

Soft Start

17pF

I1B =

ISNS

9

I2 =

4 * ILIM

3

ILIM

0.9V

R

ILIM

ILIM mirror

S/H

TO PWM COMP

4.14K

300K

I1A =

ISNS

0.17pF