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CDCF5801 Scheda tecnica(PDF) 1 Page - Texas Instruments

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Il numero della parte CDCF5801
Spiegazioni elettronici  CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

CDCF5801 Scheda tecnica(HTML) 1 Page - Texas Instruments

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FEATURES
APPLICATIONS
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24
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VDDREF
REFCLK
VDDP
GNDP
GND
LEADLAG
DLYCTRL
GNDPA
VDDPA
VDDPD
STOPB
PWRDNB
P0
P1
VDDO
GNDO
CLKOUT
NC
CLKOUTB
GNDO
VDDO
MULT0
MULT1
P2
DBQ PACKAGE
(TOP VIEW)
DESCRIPTION
CDCF5801
SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004
CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
Video Graphics
Low-Jitter Clock Multiplier:
×1, ×2, ×4, ×8
Gaming Products
Programmable Bidirectional Delay Steps of
Datacom
1.3 mUI
Telecom
Output Frequency Range of 25 MHz to
Noise Cancellation Created by FPGAs
280 MHz
Input Frequency Range of 12.5 MHz to
240 MHz
Low Jitter Generation
Single-Ended REFCLK Input With Adjustable
Trigger Level (Works With LVTTL, HSTL, and
LVPECL)
Differential/Single-Ended Output
Output Can Drive LVPECL, LVDS, and LVTTL
Three Power Operating Modes to Minimize
Power
Low Power Consumption (< 190 mW at
280 MHz/3.3 V)
Packaged in a Shrink Small-Outline Package
(DBQ)
No External Components Required for PLL
Spread Spectrum Clock Tracking Ability to
Reduce EMI (SSC)
The CDCF5801 provides clock multiplication from a reference clock (REFCLK) signal with the unique capability
to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising
edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input
detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin
the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This
unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other
CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it
provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin,
while strapping the LEADLAG pin to dc high or low. Further possible applications are:
Aligning the rising edge of the output clock signal to the input clock rising edge
Avoiding PLL instability in applications that require very long PLL feedback lines
Isolation of jitter and digital switching noise
Limitation of jitter in systems with good ppm frequency stability
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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