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MRF89XA Scheda tecnica(PDF) 52 Page - Microchip Technology |
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MRF89XA Scheda tecnica(HTML) 52 Page - Microchip Technology |
52 / 140 page MRF89XA DS70000622D-page 52 Preliminary 2010-2017 Microchip Technology Inc. 2.20.3 PACKET CONFIGURATION REGISTER DETAILS REGISTER 2-31: PKTCREG: PACKET CONFIGURATION REGISTER (ADDRESS:0x1E) (POR:0x48) R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 PKTLENF PRESIZE<1:0> WHITEON CHKCRCEN ADDFIL<1:0> STSCRCEN bit 7 bit 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown r = Reserved bit 7 PKTLENF: Packet Length Format bit 1 = Variable Length Format 0 = Fixed Length Format (default) bit 6-5 PRESIZE<1:0>: Preamble Size bits These bits indicate the size of the preamble bits to be transmitted. 11 = 4 bytes 10 = 3 bytes (default) 01 = 2 bytes 00 = 1 byte bit 4 WHITEON: Whitening/Dewhitening Process Enable bit 1 = ON 0 = OFF (default) bit 3 CHKCRCEN: Check (or Calculation) CRC Enable bit 1 = ON (default) 0 = OFF bit 2-1 ADDFIL<1:0>: Address Filtering bits These bits determine the mode of filter out the addresses of received packet. 11 = Node Address & 0x00 & 0xFF Accepted; otherwise, rejected 10 = Node Address & 0x00 Accepted; otherwise, rejected 01 = Node Address Accepted; otherwise, rejected 00 = OFF (default) bit 0 STSCRCEN: Status Check CRC Enable bit This bit checks the status or result of the CRC of the current packet (read-only). 1 = OK 0 = Not OK |
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