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TC55V4000ST-70 Scheda tecnica(PDF) 7 Page - Toshiba Semiconductor |
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TC55V4000ST-70 Scheda tecnica(HTML) 7 Page - Toshiba Semiconductor |
7 / 10 page TC55V4000ST-70,-85 2001-11-30 7/10 WRITE CYCLE 2 ( CONTROLLED) (See Note 4) Note: (1) R/W remains HIGH for the read cycle. (2) If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. CE Address R/W tWC tAS tWR tWP CE DOUT tCW VALID DATA IN tODW DIN tDS tDH tCOE Hi-Z Hi-Z (See Note 5) (See Note 5) |
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