MT9V023_17 datasheet(11/43 Pages) ONSEMI

Il numero della parte	MT9V023

Spiegazioni elettronici	1/3-Inch Wide?륷GA CMOS Digital Image Sensor

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MT9V023

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11

SERIAL BUS DESCRIPTION

Registers are written to and read from the MT9V023

through the two-wire serial interface bus. The MT9V023 is

a serial interface slave with four possible IDs (0x90, 0x98,

0xB0 and 0xB8) determined by the S_CTRL_ADR0 and

S_CTRL_ADR1 input pins. Data is transferred into the

MT9V023 and out through the serial data (SDATA) line. The

SDATA line is pulled up to VDD off-chip by a 1.5K

Ω resistor.

Either the slave or master device can pull the SDATA line

down−the serial interface protocol determines which device

is allowed to pull the SDATA line down at any given time. The

registers are 16-bit wide, and can be accessed through 16−

or 8−bit two−wire serial interface sequences.

Protocol

The two-wire serial interface defines several different

transmission codes, as shown in the following sequence:

1. a start bit

2. the slave device 8-bit address

3. a(n) (no) acknowledge bit

4. an 8-bit message

5. a stop bit

Start Bit

The start bit is defined as a HIGH-to-LOW transition of

the data line while the clock line is HIGH.

Slave Address

The 8-bit address of a two-wire serial interface device

consists of 7 bits of address and 1 bit of direction. A “0” in

the LSB of the address indicates write mode, and a “1”

indicates read mode. As indicated above, the MT9V023

allows four possible slave addresses determined by the two

input pins, S_CTRL_ADR0 and S_CTRL_ADR1.

Acknowledge Bit

The master generates the acknowledge clock pulse. The

transmitter (which is the master when writing, or the slave

when reading) releases the data line, and the receiver

indicates an acknowledge bit by pulling the data line LOW

during the acknowledge clock pulse.

No-Acknowledge Bit

The no-acknowledge bit is generated when the data line is

not pulled down by the receiver during the acknowledge

clock pulse. A no-acknowledge bit is used to terminate a

read sequence.

Stop Bit

The stop bit is defined as a LOW-to-HIGH transition of

the data line while the clock line is HIGH.

Sequence

A typical READ or WRITE sequence begins by the

master sending a start bit. After the start bit, the master sends

the slave device’s 8-bit address. The last bit of the address

determines if the request is a read or a write, where a “0”

indicates a WRITE and a “1” indicates a READ. The slave

device acknowledges its address by sending an

acknowledge bit back to the master.

If the request was a WRITE, the master then transfers the

8-bit register address to which a WRITE should take place.

The slave sends an acknowledge bit to indicate that the

register address has been received. The master then transfers

the data 8 bits at a time, with the slave sending an

acknowledge bit after each 8 bits. The MT9V023 uses 16-bit

data for its internal registers, thus requiring two 8-bit

transfers to write to one register. After 16 bits are transferred,

the register address is automatically incremented, so that the

next 16 bits are written to the next register address. The

master stops writing by sending a start or stop bit.

A typical READ sequence is executed as follows. First the

master sends the write mode slave address and 8-bit register

address, just as in the write request. The master then sends

a start bit and the read mode slave address. The master then

clocks out the register data 8 bits at a time. The master sends

an acknowledge bit after each 8-bit transfer. The register

address is automatically incremented after every 16 bits is

transferred. The data transfer is stopped when the master

sends a no-acknowledge bit. The MT9V023 allows for 8-bit

data transfers through the two-wire serial interface by

writing (or reading) the most significant 8 bits to the register

and then writing (or reading) the least significant 8 bits to

Byte-Wise Address register (0x0F0).

Bus Idle State

The bus is idle when both the data and clock lines are

HIGH. Control of the bus is initiated with a start bit, and the

bus is released with a stop bit. Only the master can generate

the start and stop bits.

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