MT9P031_17 datasheet(27/32 Pages) ONSEMI

Il numero della parte	MT9P031

Spiegazioni elettronici	1/2.5-Inch 5 Mp CMOS Digital Image Sensor

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MT9P031

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Table 17. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued)

Unit

Max

Typ

Min

Condition

Definition

Symbol

tSDSR

SDATA setup

READ

0

19.9

59.9

ns

CIN_SI

Serial interface input pin capacitance

–

3.5

–

pF

CLOAD_SD

SDATA max load capacitance

–

15

–

pF

RSD

SDATA pull-up resistor

–

1.5

–

kΩ

I/O Timing

By default, the MT9P031 launches pixel data, FV and LV

with the rising edge of PIXCLK. The expectation is that the

user captures DOUT[11:0], FV and LV using the falling edge

of PIXCLK.

See Figure 29 and Table 18 for I/O timing (AC)

characteristics.

Figure 29. I/O Timing Diagram

Data[7:0]

FRAME_VALID/

LINE_VALID

FRAME_VALID leads LINE_VALID by 609 PIXCLKs.

FRAME_VALID trails

LINE_VALID by 16 PIXCLKs.

PIXCLK

*PLL disabled for t CP

EXTCLK

tCP

tR

tEXTCLK

tF

tRP

tFP

tPD

tPFH

tPLH

tPF

tPL

Pxl _ 0

Pxl _ 1

Pxl _ 2

Pxl _ n

90 %

10 %

90 %

10 %

Table 18. I/O TIMING CHARACTERISTICS

Symbol

Definition

Condition

Min

Typ

Max

Unit

fEXTCLK1

Input clock frequency

PLL enabled

6

–

27

MHz

tEXTCLK1

Input clock period

PLL enabled

166

–

37

ns

fEXTCLK2

Input clock frequency

PLL disabled

6

–

96

MHz

tEXTCLK2

Input clock period

PLL disabled

125

–

10.4

ns

tR

Input clock rise time

0.03

–

1

V/ns

tF

Input clock fall time

0.03

–

1

V/ns

tRP

Pixclk rise time

0.03

–

1

V/ns

tFP

Pixclk fall time

0.03

–

1

V/ns

Clock duty cycle

40

50

60

%

t(PIX JITTER)

Jitter on PIXCLK

–

1.03

ns

tJITTER1

Input clock jitter 48 MHz

–

300

–

ps

tJITTER2

Input clock jitter 96 MHz

–

220

–

ps

tCP

EXTCLK to PIXCLK propagation delay

Nominal voltages

11.5

17.7

19.1

ns

fPIXCLK

PIXCLK frequency

Default

6

–

96

MHz

tPD

PIXCLK to data valid

Default

0.8

2.1

3.9

ns

tPFH

PIXCLK to FV HIGH

Default

2.8

4.3

5.9

ns

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