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MT9M131 Scheda tecnica(PDF) 32 Page - ON Semiconductor

Il numero della parte MT9M131
Spiegazioni elettronici  1/3?릋nch SOC 1.3Mp CMOS Digital Image Sensor
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Table 13. SENSOR CORE REGISTER DESCRIPTIONS (continued)
Bit Field
Read/Write
Bad
Frame
Synced to
Frame Start
Default
(Hex)
Description
R7:0 − 0x007 − Horizontal Blanking − Context A
Bits 10:0
Horizontal
Blanking A
Number of blank columns in a row when context A
is chosen (R0x0C8[0] = 0). The extra columns are
added at the beginning of a row. If set smaller than
the minimum value, the minimum value is used. With
default settings, the minimum horizontal blanking is
202 columns in full-power readout mode and
114 columns in low-power readout mode.
0xBE
Y
YM
W
R8:0 − 0x008 − Vertical Blanking − Context A
Bits 14:0
Vertical blanking A
Number of blank rows in a frame when context A is
chosen (R0x0C8[1] = 1). This number must be equal
to or larger than the number of dark rows read out in
a frame specified by R0x022.
0x11
Y
N
W
R9:0 − 0x009 − Shutter Width
Bits 15:0
Shutter width
Integration time in number of rows. In addition to this
register, the shutter delay register (R0x00C) and the
overhead time influences the integration time for
a given row time.
0x219
Y
N
W
R10:0 − 0x00A − Row Speed
Bits 15:13
Reserved
Bit 8
Invert Pixel Clock
Invert pixel clock. When set, LV, FV, and DATA_OUT
are set to the falling edge of PIXCLK. When clear,
they are set to the rising edge if there is no pixel clock
delay.
0x0
N
0
W
Bits 7:4
Delay Pixel Clock
Delay PIXCLK in half-master-clock cycles. When set,
the pixel clock can be delayed in increments of
half-master-clock cycles compared to the
synchronization of FV, LV, and DATA_OUT.
0x1
N
0
W
Bits 3:0
Pixel Clock Speed
Pixel clock period in master clocks when full−power
readout mode is used (R0x020/0x021, bit 10 = 0). In
this case, the ADC clock has twice the clock period.
If low-power readout mode is used, the pixel clock
period is automatically doubled, so the ADC clock
period remains the same for one programmed
register value. The value “0” is not allowed, and “1” is
used instead.
0x1
Y
YM
W
R11:0 − 0x00B − Extra Delay
Bits 13:0
Extra Delay
Extra blanking inserted between frames specified in
pixel clocks. Can be used to get a more exact frame
rate. For integration times less than a frame,
however, it might affect the integration times for parts
of the image.
0x0
Y
0
W
R12:0 − 0x00C − Shutter Delay
Bits 10:0
Shutter Delay
The amount of time from the end of the sampling
sequence to the beginning of the pixel reset
sequence. This variable is automatically halved in
low-power readout mode, so the time in use remains
the same. This register has an upper value defined
by the fact that the reset needs to finish prior to
readout of that row to prevent changes in the row
time.
0x0
Y
N
W


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