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MT9M114 Scheda tecnica(PDF) 7 Page - ON Semiconductor

Il numero della parte MT9M114
Spiegazioni elettronici  High?륞efinition (HD) System?륮n?륾?륝hip (SOC) Digital Image Sensor
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7
POWER-UP AND POWER-DOWN SEQUENCE
Powering up and powering down the sensor requires
voltages to be applied in a particular order, as seen in
Figure 4. The timing requirements are shown in Table 4.
The sensor includes a power-on reset feature that initiates
a reset upon power up of the sensor
Figure 4. Power-Up and Power-Down Sequence
VDD_IO
t1
VAA, VDD_PLL
EXTCLK
SCLK
SDATA
VDD, VDD_PHY
t2
t3
t4
t5
t6
t7
Table 4. POWER-UP AND DOWER-DOWN SIGNAL TIMING
Symbol
Parameter
Min
Typ
Max
Unit
t1
Delay from VDD_IO to VDD and VDD_PHY
0
50
ms
t2
Delay from VDD_IO to VAA and VDD_PLL
0
50
ms
t3
EXTCLK Activation
t2
ms
t4
First Serial Command (Notes 1, 2)
44.5
ms
t5
EXTCLK Cutoff
t6
ms
t6
Delay from VAA and VDD_PLL to VDD_IO
0
50
ms
t7
Delay from VDD and VDD_PHY to VDD_IO
0
50
ms
1. Under the condition of EXTCLK = 24 MHz and default settings with CONFIG = 1.
2. The host should poll the Command register to determine when the device is initialized.


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