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MT9M034 Scheda tecnica(PDF) 10 Page - ON Semiconductor |
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MT9M034 Scheda tecnica(HTML) 10 Page - ON Semiconductor |
10 / 39 page MT9M034 www.onsemi.com 10 Parallel Output Data Timing The output images are divided into frames, which are further divided into lines. By default, the sensor produces 968 rows of 1284 columns each. The FV and LV signals indicate the boundaries between frames and lines, respectively. PIXCLK can be used as a clock to latch the data. For each PIXCLK cycle, with respect to the falling edge, one 12−bit pixel datum outputs on the DOUT pins. When both FV and LV are asserted, the pixel is valid. PIXCLK cycles that occur when FV is de−asserted are called vertical blanking. PIXCLK cycles that occur when only LV is de−asserted are called horizontal blanking. Figure 8. Default Pixel Output Timing PIXCLK FV LV DOUT [11:0] P0 P1 P2 P3 P4 Vertical Blanking Horiz Blanking Valid Image Data Horiz Blanking Vertical Blanking Pn LV and FV The timing of the FV and LV outputs is closely related to the row time and the frame time. FV will be asserted for an integral number of row times, which will normally be equal to the height of the output image. LV will be asserted during the valid pixels of each row. The leading edge of LV will be offset from the leading edge of FV by 6 PIXCLKs. Normally, LV will only be asserted if FV is asserted; this is configurable as described below. LV Format Options The default situation is for LV to be de−asserted when FV is de−asserted. By configuring R0x306E[1:0], the LV signal can take two different output formats. The formats for reading out four lines and two vertical blanking lines are shown in Figure 9. Figure 9. LV Format Options Default Continuous LV XOR LV FV LV FV LV FV LV The timing of an entire frame is shown in Figure 10: “Line Timing and FRAME_VALID/LINE_VALID Signals”. |
Codice articolo simile - MT9M034_17 |
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Descrizione simile - MT9M034_17 |
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