AD73311L_17 datasheet(5/37 Pages) AD

Il numero della parte	AD73311L

Spiegazioni elettronici	Low Cost, Low Power CMOS

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Produttore elettronici	AD [Analog Devices]

Homepage	http://www.analog.com

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REV. A

AD73311L

–4–

Table II. Signal Ranges

Parameter

Condition

Signal Range

VREFCAP

1.2 V

± 10%

VREFOUT

1.2 V

± 10%

ADC

Maximum Input Range at VIN

1.578 V p-p

Nominal Reference Level

1.0954 V p-p

DAC

Maximum Voltage

Output Swing

Single-Ended

1.578 V p-p

Differential

3.156 V p-p

Nominal Voltage

Output Swing

Single-Ended

1.0954 V p-p

Differential

2.1909 V p-p

Output Bias Voltage

VREFOUT

TIMING CHARACTERISTICS

Limit at

Parameter

TA = –40 C to +105 C

Unit

Description

Clock Signals

See Figure 1

t1

61

ns min

MCLK Period

t2

24.4

ns min

MCLK Width High

t3

24.4

ns min

MCLK Width Low

Serial Port

See Figures 3 and 4

t4

t1

ns min

SCLK Period

t5

0.4

× t1

ns min

SCLK Width High

t6

0.4

× t1

ns min

SCLK Width Low

t7

20

ns min

SDI/SDIFS Setup Before SCLK Low

t8

0

ns min

SDI/SDIFS Hold After SCLK Low

t9

10

ns max

SDOFS Delay from SCLK High

t10

10

ns min

SDOFS Hold After SCLK High

t11

10

ns min

SDO Hold After SCLK High

t12

10

ns max

SDO Delay from SCLK High

t13

30

ns max

SCLK Delay from MCLK

(AVDD = DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted)

t1

t2

t3

Figure 1. MCLK Timing

100 AIOL

100 AIOH

CL

15pF

2.1V

TO OUTPUT

Figure 2. Load Circuit for Timing Speciﬁcations

t1

t2

t3

t13

t5

t6

t4

MCLK

SCLK

*

SCLK IS INDIVIDUALLY PROGRAMMABLE

IN FREQUENCY (MCLK/4 SHOWN HERE).

*

Figure 3. SCLK Timing

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