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AD7143 Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD7143 Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 57 page AD7143 Rev. 0 | Page 3 of 56 SPECIFICATIONS VCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CAPACITANCE-TO-DIGITAL CONVERTER Update Rate 23 25 26 ms Eight conversion stages in sequencer, decimation = 256 Resolution 16 Bit CIN Input Range1 ±2 pF No Missing Codes 16 Bit Guaranteed by design, but not production tested CIN Input Leakage 25 nA Total Unadjusted Error ±20 % Output Noise (Peak-to-Peak) 7 Codes Decimation rate = 128 3 Codes Decimation rate = 256 Output Noise (RMS) 0.8 Codes Decimation rate = 128 0.5 Codes Decimation rate = 256 Parasitic Capacitance 40 pF Parasitic capacitance to ground, per CIN input guaranteed by characterization CBULK Offset Range1 ±20 pF CBULK Offset Resolution 156.25 fF Low Power Mode Delay Accuracy 5 % % of 200 ms, 400 ms, 600 ms, or 800 ms EXCITATION SOURCE Frequency 237.5 240 262.5 kHz Output Voltage VCC V Short-Circuit Source Current 20 mA Short-Circuit Sink Current 50 mA Maximum Output Load 250 pF Capacitance load on source to ground CSHIELD Output Drive 10 μA CSHIELD Bias Level VCC/2 V LOGIC INPUTS (SCLK, SDA) VIH Input High Voltage 0.7 × VDRIVE V VIL Input Low Voltage 0.4 V IIH Input High Voltage −1 μA IIL Input Low Voltage 1 μA VIN = GND Hysteresis 150 mV OPEN-DRAIN OUTPUTS (SCLK, SDA, INT) VOL Output Low Voltage 0.4 V ISINK = −1 mA IOH Output High Leakage Current +0.1 ±1 μA POWER VCC 2.6 3.3 3.6 V VDRIVE 1.65 3.6 V ICC 0.9 1 mA In full power mode 20 μA Low power mode, converter idle, TA = 25°C 16 30 μA Low power mode, converter idle 4.5 μA Full shutdown, TA = 25°C 2.25 15 μA Full shutdown 1 CIN and CBULK are defined as follows: PLASTIC OVERLAY SENSOR BOARD CBULK CIN CAPACITIVE SENSOR |
Codice articolo simile - AD7143_17 |
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Descrizione simile - AD7143_17 |
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