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AD5171 Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD5171 Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 20 page AD5171 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS 6, 10, 11 Bandwidth –3 dB BW_5k RAB = 5 kΩ, Code = 0x20 1500 kHz BW_10k RAB = 10 kΩ, Code = 0x20 600 kHz BW_50k RAB = 50 kΩ, Code = 0x20 110 kHz BW_100k RAB = 100 kΩ, Code = 0x20 60 kHz Total Harmonic Distortion THD VA =1 V rms, RAB = 10 kΩ, VB = 0 V DC, f = 1 kHz 0.05 % Adjustment Settling Time tS1 VA= 5 V ± 1 LSB error band, VB = 0, measured at VW 5 µs OTP Settling Time12 tS_OTP VA = 5 V ± 1 LSB error band, VB = 0, measured at VW 400 ms Power-up Settling Time—Post Fuses Blown tS2 VA = 5 V ±1 LSB error band, VB = 0, measured at VW 5 µs Resistor Noise Voltage eN_WB RAB = 5 kΩ, f = 1 kHz, Code = 0x20 8 nV/√Hz RAB = 10 kΩ, f = 1 kHz, Code = 0x20 12 nV/√Hz INTERFACE TIMING CHARACTERISTICS (Applies to all parts6,12) SCL Clock Frequency fSCL 400 kHz tBUF Bus Free Time between Start and Stop t1 1.3 µs tHD;STA Hold Time (Repeated Start) t2 After this period, the first clock pulse is generated 0.6 µs tLOW Low Period of SCL Clock t3 1.3 µs tHIGH High Period of SCL Clock t4 0.6 50 µs tSU;STA Setup Time for Start Condition t5 0.6 µs tHD;DAT Data Hold Time t6 0.9 µs tSU;DAT Data Setup Time t7 0.1 µs tF Fall Time of Both SDA and SCL Signals t8 0.3 µs tR Rise Time of Both SDA and SCL signals t9 0.3 µs tSU;STO Setup Time for Stop Condition t10 0.6 µs 1Typicals represent average readings at 25°C and VDD = 5 V. 2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3VAB = VDD, Wiper (VW) = No connect. 4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6Guaranteed by design and not subject to production test. 7Different from operating power supply, power supply for OTP is used one-time only. 8Different from operating current, supply current for OTP lasts approximately 400 ms for one-time needed only. 9PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value result in the minimum overall power consumption. 11All dynamic characteristics use VDD = 5 V. 12Different from settling time after fuse is blown. The OTP settling time occurs once only. SCL SDA t1 t2 t3 t8 t8 t9 t4 t5 t9 t7 t6 t10 P PS Figure 3. Interface Timing Diagram Rev. PrC | Page 4 of 20 Preliminary Technical Data |
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