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FDG6318P Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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FDG6318P Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 5 page January 2003 2003 Fairchild Semiconductor Corporation FDG6318P Rev C (W) FDG6318P Dual P-Channel, Digital FET General Description These dual P-Channel logic level enhancement mode MOSFET are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Applications • Battery management Features • –0.5 A, –20 V. RDS(ON) = 780 m Ω @ V GS = –4.5 V RDS(ON) = 1200 m Ω @ V GS = –2.5 V • Very low level gate drive requirements allowing direct operation in 3V circuits (VGS(th) < 1.5V). • Compact industry standard SC70-6 surface mount package S G D D G S Pin 1 SC70-6 S G D D G S 6 or 3 5 or 2 4 or 1 1 or 4 2 or 5 3 or 6 The pinouts are symmetrical; pin 1 and pin 4 are interchangeable. Absolute Maximum Ratings TA=25 oC unless otherwise noted Symbol Parameter Ratings Units VDSS Drain-Source Voltage –20 V VGSS Gate-Source Voltage ±12 V ID Drain Current – Continuous (Note 1) –0.5 A – Pulsed –1.8 PD Power Dissipation for Single Operation (Note 1) 0.3 W TJ, TSTG Operating and Storage Junction Temperature Range –55 to +150 °C Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 415 °C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity .38 FDG6318P 7’’ 8mm 3000 units |
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