33996

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

10

Figure 5. Parallel Inputs SPI Control

FUNCTIONAL PIN DESCRIPTION

Chip Select (CS) Pin

The system MCU selects the 33996 to be communicated

pin is in a logic low state, data can be transferred from the MCU

to the 33996 and vise versa. Clocked-in data from the MCU is

transferred from the 33996 Shift register and latched into the

transferred from the Power Outputs Status register into the

device’s SO Shift register. The SO pin output driver is enabled

33996 to the MCU. To avoid any spurious data, it is essential

SCLK is in a logic low state.

System Clock (SCLK) Pin

The System Clock (SCLK) pin clocks the Internal Shift

registers of the 33996. The Serial Input (SI) pin accepts data

into the Input Shift register on the falling edge of the SCLK

signal, while the Serial Output (SO) pin shifts data information

out of the Shift register on the rising edge of the SCLK signal.

False clocking of the Shift register must be avoided, ensuring

validity of data. It is essential that the SCLK pin be in a logic low

reason, it is recommended, though not necessary, that the

SCLK pin is commanded to a low logic state as long as the

in a logic high state, any signal at the SCLK and SI pins is

ignored and the SO is tri-stated (high impedance).

Serial Input (SI) Pin

The Serial Input (SI) pin is used to enter one of seven serial

instructions into the 33996. SI SPI bits are latched into the Input

Shift register on each falling edge of SCLK. The Shift register is

full after 24 bits of information are entered. The 33996 operates

data integrity, exercise care not to transition SI as SCLK

transitions from high to low state (see Figure 2, page 8).

Serial Output (SO) Pin

The Serial Output (SO) pin transfers fault status data from

pin transitions to a logic low state. All faults on the 33996 are

reported to the MCU as logic [1]. Conversely, normal operating

outputs with nonfaulted loads are reported as logic [0]. On the

transferred from the Power Outputs Status register into the

device’s SO Shift register. The first eight positive transitions of

SCLK will provide Any Fault (bit 23), Overvoltage Fault (bit 22),

followed by six logic [0]s (bits 21 to 16). The next 16 successive

positive transitions of SCLK provides fault status for output 15

Parallel

Ports

MC68HCXX

Microcontroller

33996

33996

SI

SCLK

CS

SI

SO

SCLK

CS

SCLK

MISO

MOSI

Shift Register

SO

PWM1

PWM

RST

PWM

PWM2

RST

Freescale Semiconductor, Inc.

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