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HT98R068-1 Scheda tecnica(PDF) 29 Page - Holtek Semiconductor Inc |
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HT98R068-1 Scheda tecnica(HTML) 29 Page - Holtek Semiconductor Inc |
29 / 116 page Rev. 1.10 �8 �e���a�� 1�� �01� Rev. 1.10 �9 �e���a�� 1�� �01� HT98R068-1 Two Way Radio 8-Bit MCU HT98R068-1 Two Way Radio 8-Bit MCU Bit 3~0 WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable 1010: WDT disabled Other values: WDT enabled - Recommended value is 0101 If the “watchdog timer enable” is configuration option is selected, then the watchdog timer will always be enabled and the WDTEN3~WDTEN0 control bits will have no effect. Note: The WDT is only disabled when both the WDT configuration option is disabled and when bits WDTEN3~WDTEN0=1010. The WDT is enabled when either the WDT configuration option is enabled or when bits WDTEN3~WDTEN0≠1010. CTRL2 Register Bit 7 6 5 4 3 2 1 0 Name M1 M0 PLLD� AUPRST PLLEN PLLD1 PLLD0 LXTEN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 0 0 1 1 0 Bit7~6 M1, M0: PLL output frequency selection 00: 8.192MHz 01: 10.24MHz 10: 12.288MHz 11: 16.384MHz Bit5 PLLD2: PLL output frequency divider selection (For Audio Processor) 0: PLL output frequency divided by 1 1: PLL output frequency divided by 2 Bit4 AUPRST: Audio Processor hardware reset bit 1→0→1: Audio Processor reset. Bit3 PLLEN: PLL enable 0: disable 1: enable Bit2~1 PLLD1, PLLD0: PLL output frequency divider selection (For MCU) 00: useless that will be forced to “1, 1” by hardware 01: PLL output frequency divided by 1 10: PLL output frequency divided by 2 11: PLL output frequency divided by 4 Bit0 LXTEN: LXT Oscillator on/off control after execution of HALT instruction 0: LXT off in Idle mode 1: LXT on in Idle mode PLL output frequency for Audio Processor system clock (fap)and divider reference clock is according to M1, M0 setting as shown below. PLLEN M1 M0 Clock Output 0 X X LOW(Logic state) 1 0 0 8.19�MHz 1 0 1 10.�4MHz 1 1 0 1�.�88MHz 1 1 1 16.�84MHz X: Don’t ca�e |
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