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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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HT82R732 Scheda tecnica(PDF) 20 Page - Holtek Semiconductor Inc |
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HT82R732 Scheda tecnica(HTML) 20 Page - Holtek Semiconductor Inc |
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20 / 74 page  · STATUS Register Bit 76543210 Name ¾¾ TO PDF OV Z AC C R/W ¾¾ R R R/W R/W R/W R/W POR ¾¾ 0 0 xxxx ²x² unknown Bit 7, 6 Unimplemented, read as ²0² Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the ²CLR WDT² or ²HALT² instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the ²CLR WDT² instruction 1: By executing the ²HALT² instruction Bit 3 OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. System Control Registers - SYSC This register is used to provide control over various internal functions. Some of these include the Wake-up time selection, PFD control and the TBHP register enable control. · SYSC Register Bit 76543210 Name SSTC TBRC PFDC1 PFDCS ¾¾¾ PFDC0 R/W R/W R/W R/W R/W ¾¾¾ R/W POR 0000 ¾¾¾ 0 Bit 7 SSTC: wake up time selection 0: 1024 system clocks 1: 16 system clocks The SSTC bit is used to select the wake-up time for the system to wake up from the HALT mode. Bit 6 TBRC: TBHP register enable control 0: disable 1: enable Bit 5, 0 PFDC1, PFDC0 : PFD or I/O selection 00: I/O 01: I/O 10: PFD output to PB4 11: PFD output to PA3 Bit 4 PFDCS: PFD clock source 0: Timer 0 1: Timer 1 Bit 3~1 Unimplemented, read as ²0² Rev. 1.00 20 October 31, 2013 HT82R732 e-Banking 8-Bit OTP MCU |
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