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HT82A525R Scheda tecnica(PDF) 38 Page - Holtek Semiconductor Inc |
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HT82A525R Scheda tecnica(HTML) 38 Page - Holtek Semiconductor Inc |
38 / 71 page If the PDMA bit is cleared to zero and the SDMAEN bit in the MISC register is set high, then the serial DMA function will be enabled. The SBDR1 data of the SPI1 or the SBDR2 data of the SPI2, selected by the SDMSEL bit in the MISC register, will be written to FIFO3. Serial DMA In the Serial DMA mode, the SPI1 or SPI2 data, selected by SDMASEL bit, can be written to FIFO3 directly. SCLK is pin shared with the PB0 pin and used as the clock output for serial or parallel DMA function. The clock output function is controlled by the SCLKEN and CLKAUTOB bits in the CLK register. The clock output frequency, (12, 16, 24, 6, 8, 4, 3, 2 MHz), is selected by the FSCLK by configuration option. If the SBEN, SDMAEN bits are set high, and PDMA is cleared to zero, the SPI interface DMA will enter the master mode and start to send out the SCK clock. If the SPI is in the master mode and is used as a receiver, the SCK clock will be stopped automatically when FIFO3 is full and will restart again when FIFO3 is not full. If the SPI is in the slave mode and is used as a receiver, if FIFO3 is full, the SPI will stop receiving data. It will restart again if FIFO3 is not full. The frequency of the SCK is selected using the CKS, M1 and M0 bits in the SBCR register. Note that the SCK clock output will stop at a low level if the CPOL bit is set high and stop at a high level if the CPOL bit is cleared to zero. Each SPI interface can support both master or slave mode DMA. The direction of the SPI DMA is determined by the SETIO3 bit. The corresponding buffer size of 8, 16, 32 or 64 bytes is determined by bits DLEN 0~1 by configuration option. Parallel DMA In the Parallel DMA mode, HSYNC is pin shared with PA4, PCLK is pin shared with PA5 pin, the VSYNC is pin shared with PA0 pin and the Parallel DMA data D0~D7 pins are pin shared with PD0~PD7. HSYNC and the PCLK are used to synchronize the data of the parallel interface pins which are pin shared with port D. SCLK is pin shared with the PB0 pin and is used as the clock output for serial or parallel DMA functions. The clock output function is controlled by the SCLKEN and CLKAUTOB bits in the CLK register. The clock output frequency of 12, 16, 24, 6, 8, 4, 3 or 2 MHz is selected by the FSCLK configuration option. The parallel DMA function can be used in fingerprint mode or normal mode, which is selected using the PDMA_MOD bit in the CLK register. In the normal mode, the VSYNC signal of the parallel DMA received data will be ignored. In the fingerprint mode, there are two frame pixel modes, the QVGA mode (320x240 pixels) or the CIF mode (352x288 pixels). They are selected by the FIG_PIX bit in the CLK register. If the PDMA bit is set high, the parallel DMA data will be written to FIFO2, the size of which is 64x3 bytes. There is only a slave mode for the parallel DMA and the data length can be selected as 5 bits or 8 bits by configuration option. The FIFO2 buffers will start receiving data when HSYNC is set high and stop receiving data when HSYNC is cleared to zero. If FIFO2 is not full and HSYNC is cleared to zero to stop receiving data, then FIFO2 should not receive any incoming data. Only the received data in FIFO2 can be delivered to the Endpoint. Not until the next HSYNC high signal can FIFO2 start receiving data from the next buffer. If all buffers of the FIFO2 are full before HSYNC has a falling edge, this received data should be ignored. There are two Parallel DMA data selections, to receive odd Parallel DMA data only or to receive all Parallel DMA data, selected by the PDATA_SEL bit in the CLK register. HT82A525R I/O Type USB 8-Bit OTP MCU with SPI Rev. 1.80 38 March 11, 2016 |
Codice articolo simile - HT82A525R_16 |
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Descrizione simile - HT82A525R_16 |
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