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UPD48576118F1 Scheda tecnica(PDF) 11 Page - Renesas Technology Corp

Il numero della parte UPD48576118F1
Spiegazioni elettronici  576M-BIT Low Latency DRAM
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD48576118F1 Scheda tecnica(HTML) 11 Page - Renesas Technology Corp

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µµµµPD48576118F1
R10DS0257EJ0101 Rev. 1.01
Page 11 of 51
Jan. 15, 2016
Remarks 1. IDD specifications are tested after the device is properly initialized. 0°C
≤ TC ≤ 95°C; 1.7 V ≤ VDD ≤ 1.9 V,
2.38 V
≤ VEXT ≤ 2.63 V, 1.4 V ≤ VDDQ ≤ VDD, VREF = VDDQ/2
2. tCK = tDK = MIN., tRC = MIN.
3. Input slew rate is specified in Recommended DC Operating Conditions and Recommended AC
Operating Conditions.
4. IDD parameters are specified with ODT disabled.
5. Continuous data is defined as half the D or Q signals changing between HIGH and LOW every half clock
cycles (twice per clock).
6. Continuous address is defined as half the address signals between HIGH and LOW every clock cycles
(once per clock).
7. Sequential bank access is defined as the bank address incrementing by one ever tRC.
8. Cyclic bank access is defined as the bank address incrementing by one for each command access. For
BL=4 this is every other clock.
9. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions
more than per clock cycle.


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