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S5D9 Scheda tecnica(PDF) 5 Page - Renesas Technology Corp

Il numero della parte S5D9
Spiegazioni elettronici  Microcontroller
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

S5D9 Scheda tecnica(HTML) 5 Page - Renesas Technology Corp

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R01DS0303EU0100 Rev.1.00
Page 5 of 115
Nov 3, 2016
S5D9
1. Overview
1.
Overview
The S5D9 MCU integrates multiple series of software- and pin-compatible ARM®-based 32-bit MCUs that share the
same set of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU provides a high-performance ARM Cortex®-M4 core running up to 120 MHz with the following features:
 Up to 2-MB code flash memory
 640-KB SRAM
 Graphics LCD Controller (GLCDC)
 2D Drawing Engine (DRW)
 Capacitive Touch Sensing Unit (CTSU)
 Ethernet MAC Controller (ETHERC) with IEEE 1588 PTP, USBFS, USBHS, SD/MMC Host Interface
 Quad Serial Peripheral Interface (QSPI)
 Security and safety features
 Analog peripherals.
1.1
Function Outline
Table 1.1
ARM core
Feature
Functional description
ARM Cortex-M4
 Maximum operating frequency: up to 120 MHz
 ARM Cortex-M4 core:
- Revision: r0p1-01rel0
- ARMv7E-M architecture profile
- Single precision floating point unit compliant with the ANSI/IEEE Std 754-2008
 ARM Memory Protection Unit (MPU):
- ARMv7 Protected Memory System Architecture
- 8 protect regions
 SysTick timer:
- Driven by LOCO clock
Table 1.2
Memory
Feature
Functional description
Code flash memory
Maximum 2 MB of code flash memory. See section 55, Flash Memory in User's Manual.
Data flash memory
64 KB of data flash memory. See section 55, Flash Memory in User's Manual.
Memory Mirror Function (MMF)
The MMF can be configured to mirror the wanted application image load address in code flash
memory to the application image link address in the 23-bit unused memory space (memory
mirror space addresses). Your application code is developed and linked to run from this MMF
destination address. The application code does not need to know the load location where it is
stored in code flash memory. See section 5, Memory Mirror Function (MMF) in User's Manual.
SRAM
On-chip high-speed SRAM providing either parity-bit or Error Correction Code (ECC). The first
32 KB of SRAM0 is subject to ECC. Parity check is performed for other areas. See section 53,
SRAM in User's Manual.
Standby SRAM
On-chip SRAM that can retain data in Deep Software Standby mode. See section 54, Standby
SRAM in User's Manual.
Table 1.3
System (1 of 3)
Feature
Functional description
Operating modes
Two operating modes:
- Single-chip mode
- SCI or USB boot mode.
See section 3, Operating Modes in User's Manual.


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