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S5D9 Scheda tecnica(PDF) 42 Page - Renesas Technology Corp

Il numero della parte S5D9
Spiegazioni elettronici  Microcontroller
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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R01DS0303EU0100 Rev.1.00
Page 42 of 115
Nov 3, 2016
S5D9
2. Electrical Characteristics
Figure 2.9
Power-on reset timing
Figure 2.10
Reset input timing
2.3.4
Wakeup Timing
Table 2.16
Timing of recovery from low-power modes
Item
Symbol
Min
Typ
Max
Unit
Test
conditions
Recovery time
from Software
Standby mode*1
Crystal
resonator
connected
to main
clock
oscillator
System clock source is main
clock oscillator*2
tSBYMC
-
2.4*9
2.8*9
ms
Figure 2.11
The division
ratio of all
oscillators is
1.
System clock source is PLL
with main clock oscillator*3
tSBYPC
-
2.7*9
3.2*9
ms
External
clock input
to main
clock
oscillator
System clock source is main
clock oscillator*4
tSBYEX
-
230*9
280*9
μs
System clock source is PLL
with main clock oscillator*5
tSBYPE
-
570*9
700*9
μs
System clock source is sub-clock
oscillator*8
tSBYSC
-1.2*9
1.3*9
ms
System clock source is LOCO*8
tSBYLO
-1.2*9
1.4*9
ms
System clock source is HOCO clock
oscillator*6
tSBYHO
-
240*9, *10
310
*9, *10
µs
System clock source is MOCO clock
oscillator*7
tSBYMO
-
220*9
300*9
µs
Recovery time from Deep Software Standby mode
tDSBY
-
0.65
1.0
ms
Figure 2.12
Wait time after cancellation of Deep Software Standby mode
tDSBYWT
34
-
35
tcyc
Recovery time
from Software
Standby mode to
Snooze mode
High-speed mode when system clock
source is HOCO (20 MHz)
tSNZ
-
35*9, *10
71
*9, *10
μs
Figure 2.13
High-speed mode when system clock
source is MOCO (8 MHz)
tSNZ
-11*9
14*9
μs
VCC
RES
Internal reset signal
(low is valid)
tRESWP
tRESWT
RES
Internal reset signal
(low is valid)
tRESWD, tRESWS, tRESW
tRESWT


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